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Subject	Replies	Author	Latest Post
Cross clock timing analysis	2	fpeluso	11-20-2009 09:07 PM by timpe
Solved! switch name -frequency greyed out when using Synplify	1	kguy	11-20-2009 01:06 PM by kguy
can we set implementation options in ucf file?	3	jason_1997	11-20-2009 03:55 AM by jimwu
Physical Synthesis Directed Packing Error (Pack:2811)	0	chunhang	11-19-2009 11:03 PM by chunhang
Pack:679 - Unable to obey design constraints	0	yjgao	11-19-2009 06:42 PM by yjgao
Failure of derived timing constraints - main clock isn't used as a direct clock	3	sammy_verslype	11-19-2009 07:35 AM by sammy_verslype
SmartXplorer is supported only on 32-bit or 64-bit Linux platforms. Removing host from hostlist.	4	brianetscheid	11-18-2009 11:53 AM by brianetscheid
dcm in LX50T Virtex5	3	mm_uzair	11-18-2009 09:59 AM by jimwu
modular design	5	magicyang1986	11-17-2009 11:54 AM by katem
Instantiating an NCD file in ISE	2	blakaxe	11-17-2009 06:10 AM by blakaxe
Cannot implement the design using UCF in Xilinx ISE 11.1	4	piotr.gesicki	11-16-2009 01:48 PM by jimwu
Question regarding the timing contraints for the ISE In-Depth Tutorial (watch) Version 11	1	bianka_kho	11-13-2009 10:09 AM by hobson
ODDR error when porting from Virtex-5 to Virtex-6	0	shameerudheenpt	11-12-2009 08:22 AM by shameerudheenpt
PLL_ADV Unused CLKIN2	3	dhthomas	11-11-2009 12:46 PM by luis.munoz
SmartXplorer results not matched in regular ISE	4	charlesmartin	11-10-2009 07:13 AM by jimwu
NgdBuild - "missing AREA_GROUP property" in modular design flow	3	tamasgy89	11-09-2009 08:57 AM by davidd
timing analyzer BUG	6	autohzhz	11-07-2009 07:09 PM by hem_8030
How to preserve partitions	3	hithesh	11-06-2009 06:32 AM by katem
design using floorplanner	3	sridar	10-22-2009 11:19 PM by sridar
xflow and partitions	1	tamasgy89	11-05-2009 12:53 PM by katem
n00b question: Place 1018 error (non-optimal clock IOB/clock state pair)	4	evansl	11-05-2009 11:58 AM by evansl
help, how to add a constraint that only use 3 input in 4-input LUT fpga	1	hkh80652005	11-05-2009 07:12 AM by drjohnsmith
Floating point operation synthesis problem	6	nasimzahra132@hotmail.com	11-02-2009 09:56 AM by bassman59
NgdBuild:486 - Attribute "SIM_MODE" is not allowed	2	foolsun	10-30-2009 08:32 PM by viviany
Why lock_pins constraint is not working using VHDL in ISE 11.3? [ 1 2 ]	10	hoosha	10-30-2009 02:09 PM by jimwu
Alternatives for Implementation on FPGAs	2	adriangolding	10-30-2009 10:42 AM by bassman59
ERROR in PlanAhead when ExploreAhead runs.	0	shrek	10-27-2009 10:13 AM by shrek
Increasing number of unrouted nets during PAR	0	kguy	10-29-2009 07:32 AM by kguy
Place and Route Hard Macros	0	dehbaoui	10-29-2009 04:25 AM by dehbaoui
Section 12 - Configuration String Details	4	becker1	10-27-2009 03:20 PM by becker1