Others - Xilinx User Community Forums

Documentation

Downloads

Others

Mark all Posts as Read

Mark all Posts as New

Float this Board to the Top

Subscribe to this Board

Bookmark this Board

Subscribe to this Board's RSS Feed

Invite a Friend

Threaded Format

Linear Format

Sort Messages by Thread Start Date

Edit My Preferences

Front Page

Announcements

--- Win Prizes for Kudos! ---

From now on, every time you provide a good solution or post valuable information on Xilinx User Community Forums, you will be awarded Special Kudos by the Forum Administrators. Every six months, the top two Kudos winners will receive a very special prize from Xilinx! So, for a chance to claim your well-earned reward, please continue to reply to questions and post elite messages on our Forums. Your contributions are always appreciated!

Subject	Replies	Author	Latest Post
using verilog code output from MIG on Spartan 3E board	7	keithxilinx1	11-20-2009 01:14 PM by darrenger
Ise Error in DDR2 SDRAM Control for Spartan6	5	dviana	11-05-2009 11:19 AM by jspaldings
FIFO depth, independent clock	7	elvinhfrancisco	10-30-2009 07:54 AM by jprovidenza
How to simulate a design with ip core?	2	princemmf	10-26-2009 08:16 PM by princemmf
Solved! Need idea to implement ring buffer [ 1 2 ]	11	kavya@caps.fsu.edu	10-27-2009 11:05 AM by kavya@caps.fsu.edu
multiplier rdy signal?	2	wrwadley	10-20-2009 08:02 AM by wrwadley
Why I can`t download any IP solutions?	0	alex_vi	10-17-2009 01:22 AM by alex_vi
SDR SDRAM Controller using MIG (or some other core)?	2	syouschak	10-15-2009 05:57 AM by syouschak
Need to know power usage for H264 encoder	2	epatton	10-11-2009 12:31 PM by epatton
Re: LFSR design	2	gotcha25	09-30-2009 01:53 PM by gotcha25
mig2.1 ddr2 sdram controller initializaton error in my board,phy_init_done never asserted(SIM_ONLY =1 ,xc5vlx110tff1136-1 ,vcs functional simulation) ,anybody could help ?	3	rike1	09-10-2009 12:51 AM by afair0219
MCH OPB DDR SDRAM frequencies	0	kensko408	09-22-2009 09:47 AM by kensko408
Solved! QDRII simulation model	2	lagrossi	09-22-2009 06:39 AM by bebork
Is there any IP used for converting serial datas to parallel datas in the Core Generator??	2	ztr1918294	09-15-2009 10:54 AM by bassman59
Updating Ram contents (COE file) with out re-implementing a design. [ 1 2 ]	10	c1engr	09-08-2009 01:16 PM by criley23
BRAM inference	3	sridar	09-04-2009 09:10 PM by sridar
RLDRAM Addressing	0	bhargavraj	09-04-2009 04:22 AM by bhargavraj
Solved! where are MIG back-to-back read/write details for DDR ?!	2	vikkirod	09-03-2009 02:57 PM by vikkirod
Solved! How can I download MIG007 ?	5	kmitl_crsc	08-28-2009 09:49 PM by vhdl_user
Using XCL	1	vincekoskesh@hotmail.com	08-27-2009 12:15 AM by frankopitz
using the MIG generated core for DDR SDRAM	1	qureshi031	08-26-2009 08:36 AM by criley23
FIFO synchronization	0	masken	08-26-2009 01:45 AM by masken
About DDR-SDRAM controller for XUP2P	1	squaremeng	08-25-2009 02:07 PM by hgunay
SD_RAM and Spartan II	0	ali_asadzadeh	08-19-2009 11:04 PM by ali_asadzadeh
DDR2: Bursting to odd addresses	0	jcappello	08-10-2009 02:18 PM by jcappello
Solved! clocking of MIG ddr2-sdram contoller	1	migname	08-10-2009 08:28 AM by barryabrown
help : interfacing spartan 3e with ddrsdram	1	qureshi031	08-12-2009 11:31 AM by criley23
Interfacing with MIG DDR2 MC - alignment question	1	pedro.diaz	08-10-2009 01:43 PM by jcappello
External Memory controller for ISSI RAM device IS61LV25616AL	0	wdeepak	08-02-2009 10:30 PM by wdeepak
Question on Block Memory Generator Core	0	1984john	08-06-2009 01:26 AM by 1984john