|
| |||||||||||||||||||||||||||||||||
| |||||||||||||||||||||||||||||||||
| Xilinx User Community Forums | |||||||||||||||||||||||||||||||||
| |||||||||||||||||||||||||||||||||
| Announcements | |||||||||||||||||||||||||||||||||
|
--- Win Prizes for Kudos! ---
|
|||||||||||||||||||||||||||||||||
| Subject | Replies | Author | Kudos | Rating | Latest Post | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
 |
Downloading ISF and EDK
- (11-22-2009 07:57 AM)
Location: Installation Hi, I'am trying to download ISF and EDK software 10.1 SP3, but i didn't succeed. I went to Downloads page and they asked me to fill in the from, the problem is that they refuse my adress, and i |
0 | mda |
11-22-2009 07:57 AM by mda |
|||||||||||||||||||||||||||||
|
XPS can not find the USB cable on Vista 64 bits
- (11-22-2009 04:38 AM)
![[URL]](/i/skins/default/subject_has_url.gif "This message contains a hyperlink"){kind=small}
Location: Installation Dear all, I try to download program through XPS, but unluckily I got the message as follows: Info: Cable connection failed Info: Connecting to cable <Usb port - USB 24) Info: |
0 | vonbk |
11-22-2009 04:38 AM by vonbk |
|||||||||||||||||||||||||||||
|
Why Need To Use XIntc_RegisterHandler() ?
- (11-22-2009 12:32 AM)
![[ATTACHMENT]](/i/skins/default/subject_has_attachment.gif "This message contains an attachment"){kind=small}
Location: EDK and Platform Studio Good evening sir, I have one question XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR, |
0 | moraali |
11-22-2009 12:32 AM by moraali |
|||||||||||||||||||||||||||||
|
How to design a two Virtex-6's power supply circuit?
- (11-22-2009 12:03 AM)
Location: Virtex® Family FPGAs Normal 0 7.8 pt 0 2 false false false EN-US ZH-CN X-NONE |
1 | mrpp |
11-22-2009 06:48 AM by drjohnsmith |
|||||||||||||||||||||||||||||
|
Business & Personal Web hosting Packages.
- (11-22-2009 12:01 AM)
Location: General Technical Discussion I wonder if someone know from where I can get a business or personal web packages, email packages or domain registration at one place with smart utilities. Hosting Company must be in local Middle |
0 | salmank502 |
11-22-2009 12:01 AM by salmank502 |
|||||||||||||||||||||||||||||
|
convert a bootoadable SREC file to something that iMPACT can write to flash (mcs?)
- (11-21-2009 10:59 PM)
Location: General Technical Discussion I am building a project that boots off of the flash memory on an Avnet virtex 5 FXT evaluation board ( http://www.xilinx.com/products/devkits/aes_v5fxt_evl30-avnet.htm ) I am |
0 | sfrisbie |
11-21-2009 10:59 PM by sfrisbie |
|||||||||||||||||||||||||||||
|
acessing internal signals using chipscope
- (11-21-2009 06:47 PM)
Location: Others Hi , i have some number of modules in my design , i have connected this design to PPC , now i want an internal signal of one module to be observed. After connecting chipscope if open |
1 | onkarkk1 |
11-21-2009 07:46 PM by hem_8030 |
|||||||||||||||||||||||||||||
|
Problem with Embedded tri-mode ethernet
- (11-21-2009 04:07 PM)
Location: Connectivity Hello everybody, I am using Xilinx Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper 1.5 to send out UDP packets to 1 Gbps using SGMII. I have modified the |
0 | atarazona |
11-21-2009 04:07 PM by atarazona |
|||||||||||||||||||||||||||||
|
Virtex2 pro dual port block ram
- (11-21-2009 02:13 PM)
Location: Virtex® Family FPGAs Hi I am currently working with virtex 2 pro fpga and want to use the dual port ram, the problem, I am having is that in simulation it shows right results while when I put it on the |
0 | mawais |
11-21-2009 02:13 PM by mawais |
|||||||||||||||||||||||||||||
|
XUPV5-LX110T initial configuration
- (11-21-2009 11:19 AM)
Location: Virtex® Family FPGAs Hi, Before changing the Xilinx's company initial configuration in the XUPV5-LX110T board by uploading new projects in the FPGA. I need to know how can I restore the initial |
0 | gw |
11-21-2009 11:19 AM by gw |
|||||||||||||||||||||||||||||
|
Adding SDRAM to project
- (11-21-2009 09:23 AM)
Location: Virtex® Family FPGAs Hey Everyone, I am using a Virtex II Pro and I am trying to start a new project and use the SDRAM as my memory for Instruction, Data, and Stack/Heap sections for the Peripheral |
1 | jorgy |
11-21-2009 06:31 PM by hem_8030 |
|||||||||||||||||||||||||||||
|
Maximum number of microblaze
- (11-21-2009 09:10 AM)
Location: Others Hi All, I was studying on microblaze when I found out that there is no information on how many micorblaze that can be instantiated on a particular FPGA say for the Spartan series. I |
4 | amelia.azman |
11-22-2009 04:08 AM by goran_bilski |
|||||||||||||||||||||||||||||
|
Xilinx Platform Studio licence ERROR
- (11-21-2009 08:46 AM)
![[IMG]](/i/skins/default/subject_has_image.gif "This message contains an image"){kind=small}
Location: EDK and Platform Studio Hello friends, I have a problem with my xilinx platform studio licence. I have a Spartan 3A DSP 1800A Embedded Development Kit I have a licence for EDK as you see in picture ( licence.jpg |
1 | ignorius |
11-21-2009 10:30 PM by jimbrady |
|||||||||||||||||||||||||||||
|
Simple Uart Interrupt Mode Problem (Please Help)
- (11-21-2009 05:52 AM)
Location: EDK and Platform Studio Good evening, Previously the uart was created in a polling mode (Original\ML401\TestApp_Peripheral\src\Code_Header\xuartlite_send_or_recv.c), which only receive |
2 | moraali |
11-21-2009 05:54 AM by moraali |
|||||||||||||||||||||||||||||
|
Need help for Xapp1052 GUI(VisualC) project !!!
- (11-21-2009 01:51 AM)
Location: PCI Express Hello Everyone ... I installed the driver (pcie_demo.sys) and the Performance Demo for PCIe.exe is working now ! I have to develop an user application like "Performance Demo for PCIe" by |
3 | majid_amk |
11-22-2009 07:57 AM by lacirta |
|||||||||||||||||||||||||||||
|
Problem with USB to Serial adaptor
- (11-21-2009 12:10 AM)
Location: Xilinx Boards and Kits Hi, I am trying to run the peripheral test app on a Nexys 2 board with its Serial port connected to a Trendnet USB to serial adapter (TU-S9) conencted to my laptop. But I |
2 | karvi_in |
11-22-2009 01:13 AM by karvi_in |
|||||||||||||||||||||||||||||
|
Building a 24 hour clock for school project
- (11-20-2009 05:36 PM)
Location: General Technical Discussion Hi All I am attempting to construct a 24 hour clock for a school project . I have set up the counters etc , hours , minutes seconds , |
0 | trevoooor |
11-20-2009 05:36 PM by trevoooor |
|||||||||||||||||||||||||||||
|
IP core generator??
- (11-20-2009 02:29 PM)
Location: Spartan® Family FPGAs Hi all, I use "ise 6" in order to program XC2S200E PQ208 FPGA. For a program, i need a fifo. But ise 6 doesn't have FIFO generator in IP core generator. |
0 | cenkalbayrak |
11-20-2009 02:29 PM by cenkalbayrak |
|||||||||||||||||||||||||||||
|
Building my own ACE file from the ML505 Getting Started Guide without the EDK
- (11-20-2009 02:16 PM)
Location: Xilinx Boards and Kits Hi, I'm trying to build an ACE file for button_led_test_hw.bit as specified in the Getting Started Guide. I can build it with xmd genace in the EDK, but I cannot build it correctly with |
0 | yeemanb |
11-20-2009 02:16 PM by yeemanb |
|||||||||||||||||||||||||||||
|
 Solved!
switch name -frequency greyed out when using Synplify
- (11-20-2009 01:01 PM)
Location: Implementation I was wondering why the switch -frequency is disabled by default when using Synplify no matter which design goal or strategy I select. As a consequence, Synplify assumes a default frequency of 156 |
1 | kguy |
11-20-2009 01:06 PM by kguy |
|||||||||||||||||||||||||||||
|
ML505 Ethernet
- (11-20-2009 12:46 PM)
Location: Xilinx Boards and Kits I've purchased an ML505, and I've tried the web server demo that comes with it. My computer detects it and establishes a connection but I'm unable to bring up a webpage at the indicated address (I |
1 | jonathan.ross |  |
11-20-2009 03:44 PM by jimwu |
||||||||||||||||||||||||||||
|
ML-403 base system builder
- (11-20-2009 08:27 AM)
Location: Virtex® Family FPGAs Im trying so simply get a working system loaded onto my board and run an example project. Im selecting the ML-403 eval board as the template and choosing the default values for pretty much |
1 | natebailey |
11-21-2009 06:56 AM by hem_8030 |
|||||||||||||||||||||||||||||
|
Problems with adding IIC IP core from IP catalog
- (11-20-2009 07:47 AM)
Location: EDK and Platform Studio Hello! I am aware of the fact, that this is a newbie question. Anyway, I am having problems with adding the Xilinx IIC IP core to my Microblaze project. Here's what I do: I am |
2 | sepher |
11-21-2009 03:22 AM by stone9502 |
|||||||||||||||||||||||||||||
|
ML505/ML506/ML507 Err LED - Too much blinking
- (11-20-2009 07:41 AM)
Location: Xilinx Boards and Kits Hi, According to the "Getting Started Tutorial" for the ML50x boards: When the CF card is ejected or not installed, the System ACE “Err” LED |
1 | mattfishburn |
11-20-2009 09:14 AM by austin.lesea |
|||||||||||||||||||||||||||||
|
Acknowledging Interrupts
- (11-20-2009 06:20 AM)
Location: Embedded Linux All, I have written a custom device driver for a peripheral contained with a Virtex 4 FPGA. I have and interrupt that fires when a FIFO becomes full. I would like to know at what |
1 | dhanisch |
11-20-2009 08:05 AM by linnj |
|||||||||||||||||||||||||||||
|
Generic instanciation of a module ?
- (11-20-2009 05:47 AM)
Location: General Technical Discussion Hello, I have a vhdl module i would like to instanciate several times. In order to be able able to easaly change the number of module i would like this instanciation to be generic... |
1 | guilvard |
11-20-2009 09:01 AM by bassman59 |
|||||||||||||||||||||||||||||
|
Solved!
Which port to connect stepper motor control circuitry (XUPV2P)
- (11-20-2009 05:27 AM)
Location: Virtex® Family FPGAs Hello I'm new to FPGAs , i have worked on VHDL though and know the process to program to the thing as well . I have a task to connect my XUPV2P board to stepper |
2 | munis |
11-20-2009 09:02 AM by munis |
|||||||||||||||||||||||||||||
|
integation of edk and ise
- (11-20-2009 05:03 AM)
Location: EDK and Platform Studio |
1 | shahulakthar |  |
11-21-2009 06:41 PM by hem_8030 |
||||||||||||||||||||||||||||
|
How to set TXPOLARITY for XPS_LL_TEMAC
- (11-20-2009 04:52 AM)
Location: Connectivity I have XPS_LL_TEMAC(virtex 4 hard temac is used) with 1000BASE-X physical interface in xps project. Is there some possibility to set TXPOLARITY or RXPOLARITY for RocketIO transceiver ? Thanks. Milan |
0 | mzamostny |
11-20-2009 04:52 AM by mzamostny |
|||||||||||||||||||||||||||||
|
Spartan-3A DSP 1800A UG486
- (11-20-2009 04:33 AM)
Location: Spartan® Family FPGAs I have been trying to do the example that are on the UG486 (v1.4) document [Spartan-3A DSP 2SD1800A MicroBlaze Processor Edition Kit Reference Systems]. The first example which |
1 | thamistein |
11-20-2009 06:58 AM by hem_8030 |
|||||||||||||||||||||||||||||
| Legend | |||||||||||||||||||||||||||||||||
| |||||||||||||||||||||||||||||||||
| |||||||||||||||||||||||||||||||||
| |||||||||||||||||||||||||||||||||
