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--- Win Prizes for Kudos! ---
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My XPS timer fails to work
- (11-07-2009 05:07 AM)
Location: EDK and Platform Studio I downloaded the code from the xilinx web, and tried the Lab 5 – SDK Lab. But I found that the timer didn't work on my ML505 board. I tried to read the load register of timer counter 0 after |
0 | zuoyu |
11-07-2009 05:07 AM by zuoyu |
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More basic than "hello world", this bare bones intro project blinks a single LED.
- (11-06-2009 08:13 PM)
Location: PicoBlaze Here is a bare bones project using the picoblaze. It toggles an LED. It uses a clock in, a reset in (which is optional), and an LED output. Just about every evalutation board has at least a |
1 | greglondon |
11-06-2009 08:16 PM by greglondon |
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Stuck with orignal code of KCPSM3
- (11-06-2009 05:35 PM)
Location: PicoBlaze hi there, i have downloaded kcpsm3 for my xc3s700a fpga. But wothout changing anything, i made a project and added files in it, all files of verilog have been added, i am using ISE 11.1. As |
4 | frozen_relationships |
11-06-2009 06:30 PM by greglondon |
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Looking for documentation of NGC/NGD/NCD file format
- (11-06-2009 02:07 PM)
Location: General Technical Discussion Hello! I'm wondering if there is any documentation available on the format of the NGC/NGD/NCD files? If anyone can point me to something, that'd be greatly appreciated! |
0 | ti-uni-bonn |
11-06-2009 02:07 PM by ti-uni-bonn |
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Swithing between Xilinx ISE versions using setx.exe
- (11-06-2009 01:29 PM)
![[URL]](/i/skins/default/subject_has_url.gif "This message contains a hyperlink"){kind=small}
Location: Installation Swithing between Xilinx ISE versions requires chaning an environment variable(s) to point to the correct version. The manual process is tedious (right click My Computer, Properties, Advanced, |
0 | jghelani1 |
11-06-2009 01:29 PM by jghelani1 |
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ISE v11.3 PAR with embedded processors errors out- unable to modify the file system.xmp
- (11-06-2009 01:24 PM)
Location: EDK and Platform Studio When attempting to perform a Xilinx ISE 11.3 Place and Route with embedded processors, I get an error stating it couldn't modify the file system.xmp (see transcript below). The file in question is |
1 | jghelani1 |
11-06-2009 08:29 PM by hem_8030 |
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PCB signal integrety of "T"ed clock for feedback and deskew
- (11-06-2009 10:57 AM)
Location: General Technical Discussion I am designing my own board that is roughly based on the ML507. This design includes a synchronous ZBT SRAM chip, just like the ML507. The ML507's FPGA (Virtex5) uses external clock |
0 | bryan.althouse |
11-06-2009 10:57 AM by bryan.althouse |
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Help a FPGA first timer
- (11-06-2009 10:54 AM)
Location: Virtex® Family FPGAs Hi ! This is my first post here! Well i need your opinion on some good books and material (links would be useful) through which i can start the development on XUP2VP kit i have in my |
0 | munis |
11-06-2009 10:54 AM by munis |
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PCI Bridge configuration help needed
- (11-06-2009 09:20 AM)
Location: Connectivity Hi, Has any1 used the PCI PLB Bridge core to implement a target system? I want to implement a simple system using microblaze to receive data from PCI and process it. I'm having problems in |
0 | jmonteiro-dme |
11-06-2009 09:20 AM by jmonteiro-dme |
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Jitter in hold time analysis?
- (11-06-2009 09:07 AM)
Location: Timing Analysis I notice that trce is adding clock jitter into hold time checks. This is incorrect isn't it? For my path below the clock to the destination FF does go through a DCM first, so I'm |
2 | markcurry |
11-06-2009 10:31 AM by markcurry |
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How to interpret the resource usage statistics of Virtex5 xs240t, I am not sure it can be impelemted or not
- (11-06-2009 08:13 AM)
Location: Virtex® Family FPGAs I had a design on Virtex5 sx240t. I use the simulink “estimation” to evaluate the resource usage statistics of the design. The result is shown as following: |
2 | punkmama |
11-06-2009 08:58 AM by punkmama |
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Falling Edge Register
- (11-06-2009 05:30 AM)
Location: Timing Analysis Hi all, My design is working in positive edge of clk except in a two shift registers which are working in falling edge of the same clock. The idea is to fetch the data from BRAM and shift the |
3 | sridar |
11-06-2009 08:38 PM by sridar |
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ISERDES problem in V5
- (11-06-2009 04:53 AM)
Location: Virtex® Family FPGAs Hello,I have a problem with ISERDES working in V5 FPGAs. The receiver works in DDR_LVDS mode and the frequency or bit clock rise up to 480MHz. ISERDES neads two clock in DDR mode,clk |
2 | qusuperxilinx |
11-07-2009 03:35 AM by qusuperxilinx |
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Testbench used for functional simulations can not be selected when swithing over to Post Map and Post Route simulations in ISE 11.3
- (11-06-2009 03:19 AM)
Location: Simulation and Verification After having done my functional simulations via Modelsim I want to do timing simulations with the generated Post-Map and Post-Route netlists in ISE 11.3. But when I select in the ISE 11.3 Design |
2 | prkroon |
11-07-2009 02:53 AM by prkroon |
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How to use the USB port on ml501 (Virtex 5) ?
- (11-06-2009 01:10 AM)
Location: EDK and Platform Studio Hello, I'm very new to FPGAs and I have to connect a webcam to my ml501 board (Virtex 5). But in XPS there's a padlock with a $ on the XPS_USB2_Peripheral :/ Can I use the USB port anyway |
0 | jerepain |
11-06-2009 01:10 AM by jerepain |
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CoreGen & Ubuntu Video Problem
- (11-05-2009 10:46 PM)
Location: Design Entry Hi. I realize Ubuntu is not a supported OS, but I have been running WebPack 11.1 on both Ubuntu 9.04 and 9.10 without problems until I tried to run CoreGen. When I open the CoreGen |
0 | stonewalker |
11-05-2009 10:46 PM by stonewalker |
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TIMING analyzer clock path skew BUG
- (11-05-2009 10:23 PM)
![[ATTACHMENT]](/i/skins/default/subject_has_attachment.gif "This message contains an attachment"){kind=small}
Location: Timing Analysis I use the ISE 9.1, and I find there is a report BUG for the timing analyzer: in the twr, the clock path skew are different between setup and hold path, and one skew value is error. in |
3 | autohzhz |
11-07-2009 01:45 AM by drjohnsmith |
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timing analyzer net skew problem
- (11-05-2009 09:45 PM)
Location: Timing Analysis could you help me solve problem I encounted the following timing analyzer report, I wonder the tool how to caculate the various skew. examples are as followings: |
0 | autohzhz |  |
11-05-2009 09:45 PM by autohzhz |
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simulink system period effect in HDL netlist generation
- (11-05-2009 09:43 PM)
Location: DSP Tools Hi! What's the effect of simulink system period in generating HDL netlist in system generator? I mean is it going to affect the way the HDL netlist is being generated. If |
0 | maharjanmilan |
11-05-2009 09:43 PM by maharjanmilan |
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Generic Comparator Design using VHDL
- (11-05-2009 09:43 PM)
Location: General Technical Discussion Hi all, I ve designed a generic VHDL comparator in two ways. Total number of Inputs are N, which is always be 2^n (n=2,3,4..). 1.Comparing the first and second input and the result is |
8 | sridar |
11-07-2009 01:43 AM by drjohnsmith |
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Criteria to select FPGA
- (11-05-2009 07:46 PM)
Location: General Technical Discussion Hello friends, How can we select an FPGA for our application..like what kind of protocol we should follow in selecting them.. |
2 | pradeepkumar481 |
11-06-2009 02:14 PM by jimbrady |
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can we set implementation options in ucf file?
- (11-05-2009 06:05 PM)
Location: Implementation Hi friends,I want to set some implementation options and put them in a file so I needn't set them each time that I build a new project.How to do it?Can we put the options in ucf |
2 | jason_1997 |
11-06-2009 09:36 PM by jason_1997 |
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2 microblaze cores connected Via FSL in the new EDK 11.1
- (11-05-2009 04:15 PM)
Location: EDK and Platform Studio Hello everyone, I'm working on a project that connects 2 microblazes via FSL. I'm using the new version of EDk, 11.1 so basically, this new version supports the dual core design in the BSB. |
1 | nadidjka |
11-06-2009 04:27 AM by goran_bilski |
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Error when flashing a partial bitstream with iMPACT
- (11-05-2009 02:59 PM)
Location: Spartan® Family FPGAs I am having trouble flashing a partial bitstream on a Spartan 3A starter kit with iMPACT. I made a simple counter design, and used FPGA Editor to modify a single lookup table. Both |
0 | joeantoon |
11-05-2009 02:59 PM by joeantoon |
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trying simple LED toggle with picoblaze, getting lots of warnings
- (11-05-2009 12:43 PM)
Location: PicoBlaze I'm trying to get picoblaze to work with my environment for the first time. I'm using the KCPSM3 Release 8a - 4th August and I'm using ISE release 10.1.03 When I try to |
7 | greglondon |
11-06-2009 06:49 PM by greglondon |
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Implementation of TFTP on virtex5 ml507
- (11-05-2009 11:53 AM)
Location: EDK and Platform Studio Hello all, I am trying to setup an ethernet connection b/w FPGA and host comp and would like to send some array of values to host computer that are undergone manipulations in FPGA . If i am |
3 | kavya@caps.fsu.edu |
11-06-2009 11:28 AM by patoh |
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Xilinx Spartan 2E XC2S200E PQ208AGT0345 pins?
- (11-05-2009 10:17 AM)
Location: Spartan® Family FPGAs Do you have XC2S200E 's pin connections?? Is there anybody who have the shematic of the pin connection?? |
1 | cenkalbayrak |
11-05-2009 10:38 AM by austin.lesea |
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Shift operations "<< or >>" in C without adding the barrel shifter core to Microblaze
- (11-05-2009 10:02 AM)
Location: EDK and Platform Studio Hello, I'm just using the shift left " << " and shift right operations " >> " in a code I'm implementing to run on Microblaze, however I didn't add the |
3 | walid_farid |
11-06-2009 04:31 AM by goran_bilski |
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Spartan6 LVDS_25 inputs not permitted in banks 1 and 3 on FGG484 part?
- (11-05-2009 09:37 AM)
Location: Spartan® Family FPGAs Hi, I am using the PlanAhead tool to do some pin mapping, and it is reporting that Banks 1 and 3 of a Spartan6 sc6slx150-2fgg484 are not capable of supporting LVDS_25 for inputs or outputs. |
0 | kieran_wall |
11-05-2009 09:37 AM by kieran_wall |
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Can't write to plbv46_pci PCI Bridge core registers
- (11-05-2009 08:08 AM)
Location: Connectivity Hi, I have a plbv46_pci core to interface a 32bPCI slot on a PC. When running the Peripheral test, the test fails when writing a value to a configuration register of this core. The read |
0 | jmonteiro-dme |
11-05-2009 08:08 AM by jmonteiro-dme |
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