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    <title>The ‘Programmable Imperative’</title>
    <link>http://forums.xilinx.com/t5/PLD-Blog/The-Programmable-Imperative/ba-p/37849</link>
    <description>&lt;p&gt;What are we talking about? Is this something new? Or is this something that has been around for 25 years, and has suddenly become more important?&lt;br /&gt;&lt;br /&gt;What Is It?&lt;br /&gt;&lt;br /&gt;If you look at the &amp;lsquo;programmable imperative&amp;rsquo; from a customer&amp;rsquo;s point of view, you find that they wish to achieve more with less, to reduce risks wherever possible, and to be able to differentiate their product from their competitors. In the current market, customers wish to strike a balance between:&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;blockquote&gt;&lt;p&gt;&lt;strong&gt;design challenges&lt;/strong&gt; (such as cost, power, performance and density), and&lt;/p&gt;&lt;/blockquote&gt;&lt;blockquote&gt;&lt;p&gt;&lt;strong&gt;business challenges&lt;/strong&gt; (such as fickle market demands, tight engineering budgets, escalating ASIC and ASSP non-recurring engineering costs, and ever spiraling complexities).&lt;/p&gt;&lt;/blockquote&gt;&lt;p&gt;&amp;nbsp;From a Xilinx perspective, the programmable imperative represents a two-fold commitment:&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;blockquote&gt;&lt;p&gt;first, to deliver programmable silicon innovations that supply industry-leading value for every comparison point (price, power, performance, density, features, and programmability), and&lt;/p&gt;&lt;/blockquote&gt;&lt;blockquote&gt;second, to provide customers with simpler, smarter and more strategically viable design platforms that reduce the time spent by creating the infrastructure of an application and allowing them more time to create their own unique product.&lt;br /&gt;&lt;/blockquote&gt;&lt;p&gt;The result is a better product, produced in less time, at less cost.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;What is Different?&lt;/p&gt;&lt;p&gt;&amp;nbsp;&lt;/p&gt;&lt;p&gt;The mid-range Xilinx&amp;reg; FPGA device is now fast enough and large enough to do what used to be the sole domain of the ASIC. This is a big change over the time when the devices were either too small, too slow, or both.&lt;br /&gt;&amp;nbsp;&lt;br /&gt;&lt;br /&gt;Risk, and the Cost of Failure&lt;br /&gt;&lt;br /&gt;Given the present business climate, having a solution that allows problems in the field to be fixed by updating and downloading a new bit file delivers a product more in line with the model for software. Some customers actually plan on leaving room in their FPGA to provide space for features that they plan to sell as add-ons into their markets in the future. Their products are always &amp;ldquo;fresh&amp;rdquo; and capable of providing extra value.&lt;br /&gt;&lt;br /&gt;The ASIC solution, in comparison, is a &amp;ldquo;fire and forget&amp;rdquo; solution: you have one chance, and you either succeed momentarily (no possibility of further revenue), or fail.&lt;br /&gt;&lt;br /&gt;&lt;br /&gt;Austin Lesea&lt;/p&gt;</description>
    <pubDate>Fri, 08 May 2009 22:31:14 GMT</pubDate>
    <dc:creator>austin.lesea</dc:creator>
    <dc:date>2009-05-08T22:31:14Z</dc:date>
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      <title>The ‘Programmable Imperative’</title>
      <link>http://forums.xilinx.com/t5/PLD-Blog/The-Programmable-Imperative/ba-p/37849</link>
      <description>What are we talking about? Is this something new? Or is this something that has been around for 25 years, and has suddenly become more important?</description>
      <pubDate>Fri, 08 May 2009 22:31:14 GMT</pubDate>
      <guid>http://forums.xilinx.com/t5/PLD-Blog/The-Programmable-Imperative/ba-p/37849</guid>
      <dc:creator>austin.lesea</dc:creator>
      <dc:date>2009-05-08T22:31:14Z</dc:date>
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