topic Re: Math operations on unsigned (adding) in FPGA Configuration
https://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1125592#M18234
<P><U>As you said, I had a problem with communication.</U></P><P>I was skipping some samples and jumping to the 3rd next sample instead of the next:</P><P>Current sample: #3</P><P>Next Sample: #2 (should be #4 but it goes to #4, then #1, then #2)</P><P>This gave me a wrong illusion.</P>Tue, 07 Jul 2020 15:16:06 GMTMason12020-07-07T15:16:06ZMath operations on unsigned (adding)
https://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1122680#M18129
<P>I was using integers for my VHDL code but then I switched to unsigned because of the feedback I got <A href="https://forums.xilinx.com/t5/FPGA-Configuration/Converting-an-integer-into-unsigned/m-p/1113452#M17689" target="_blank" rel="noopener">here</A>. In order to make sure I am doing the right thing, I tried to produce a ramp and send it to my MATLAB plotting code. I wrote the VHDL code in a component, here is the code I have inside the component:</P><PRE>library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SinWGen is
Port (
spi_adc_cs_b : in std_logic;
sin : out unsigned (15 downto 0);
cos : out unsigned (15 downto 0);
state_param : in integer range 0 to 3);
end SinWGen;
architecture Behavioral of SinWGen is
begin
WaveGen: process(spi_adc_cs_b)
variable cnt : unsigned (15 downto 0) := (others => '0');
variable tst : unsigned (15 downto 0) := (12 => '1', others => '0');
begin
if(rising_edge(spi_adc_cs_b)) then
if(state_param = 1) then
if(cnt < 4000) then
sin <= cnt;
cnt:= cnt + 1000;
else
sin <= (others => '0');
cnt := (others => '0');
end if;
end if;
end if;
end process WaveGen;
end Behavioral;</PRE><P>This is the section that I am concerned with:</P><LI-CODE lang="markup"> if(rising_edge(spi_adc_cs_b)) then
if(state_param = 1) then
if(cnt < 4000) then
sin <= cnt;
cnt:= cnt + 1000;
else
sin <= (others => '0');
cnt := (others => '0');
end if;
end if;
end if;</LI-CODE><P>I expect the output "sin" to be a ramp with 1000 steps which goes to 4000 and then comes back to zero. It goes exactly opposit, starts from 4000, goes down to zero in 1000 steps!</P><P>I changed the 4000 and 1000 to unsigned (i.e. "BinaryData") and re-ran the code but the results are the same. So,</P><P> </P><P>- Is this how I should be adding unsigned to another number?</P><P>- Is it ok if I use integers for these situations (because they are more straightforward) or do I have to convert my numbers to unsigned?</P><P>Thank you in advance for your help.</P><P> </P><P> </P><P> </P>Mon, 29 Jun 2020 19:40:31 GMThttps://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1122680#M18129Mason12020-06-29T19:40:31ZRe: Math operations on unsigned (adding)
https://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1122682#M18130
<P>Make cnt a signal instead of a variable. </P>Mon, 29 Jun 2020 19:49:10 GMThttps://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1122682#M18130bruce_karaffa2020-06-29T19:49:10ZRe: Math operations on unsigned (adding)
https://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1122686#M18131
<P><LI-USER uid="89438"></LI-USER> </P><P>That will make little difference here, as the assignment to cnt is done after the assigned of sin <= cnt; So the cnt will be a register as will sin. The code shows cnt incrementing in steps of 1000 up to 4000</P><P><LI-USER uid="279640"></LI-USER> </P><P>Why are you using the chip select signal as a clock?</P>Mon, 29 Jun 2020 20:38:30 GMThttps://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1122686#M18131richardhead2020-06-29T20:38:30ZRe: Math operations on unsigned (adding)
https://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1122701#M18132
<P>Long story short: I get a defined number of data and send it to an MCU, I am producing the CS! and SCK locally and use CS! as my reference here because it can easily count the number of samples that I get. In other words, the SPI is my core operation here and I prefer to use its clock for side operations as well. Let me know if this is the answer you were expecting. Thanks for your help. </P>Mon, 29 Jun 2020 21:06:00 GMThttps://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1122701#M18132Mason12020-06-29T21:06:00ZRe: Math operations on unsigned (adding)
https://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1123178#M18149
<P>I changed the code and converted the variable to signal, I also copied the code into a top module, here is how it looks like now:</P><PRE>library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Top is
Port ( clk : in STD_LOGIC);
end Top;
architecture Behavioral of Top is
signal cnt : unsigned (15 downto 0) := (others => '0');
signal sin : unsigned (15 downto 0);
begin
WaveGen: process(clk)
-- variable cnt : unsigned (15 downto 0) := (others => '0');
variable tst : unsigned (15 downto 0) := (12 => '1', others => '0');
begin
if(rising_edge(clk)) then
if(cnt < "0000111110100000") then
sin <= cnt;
cnt<= cnt + "0000001111101000";
else
-- sin <= (others => '0');
cnt <= (others => '0');
end if;
end if;
end process WaveGen;
end Behavioral;</PRE><P>Then, I simulated the code. Here are the simulation results:</P><P><span class="lia-inline-image-display-wrapper lia-image-align-center" image-alt="wave.PNG" style="width: 999px;"><img src="https://forums.xilinx.com/t5/image/serverpage/image-id/78277i2FBFA6B8724B3249/image-size/large?v=1.0&px=999" title="wave.PNG" alt="wave.PNG" /></span></P><P> </P><P>Which seems correct. But when I run the code and see the results in MATLAB, I see the following (normalized to a 3.3 V reference):</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="untitled.jpg" style="width: 560px;"><img src="https://forums.xilinx.com/t5/image/serverpage/image-id/78278iDC9A130BC19823C0/image-size/large?v=1.0&px=999" title="untitled.jpg" alt="untitled.jpg" /></span></P><P> </P><P>I really think my communication code does not have the capability of flipping the data before sending them. It is quite strange that my staircase has a negative ramp while the simulation shows the opposite. Also,</P><P>"0000111110100000" = 4000</P><P>"0000001111101000" = 1000</P><P> </P>Tue, 30 Jun 2020 18:36:52 GMThttps://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1123178#M18149Mason12020-06-30T18:36:52ZRe: Math operations on unsigned (adding)
https://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1123224#M18151
<P><LI-USER uid="279640"></LI-USER> </P>
<P>Some thoughts:</P>
<OL>
<LI>Your latest VHDL works! That is, cnt will increment as 0, 1000, 2000, 3000, 4000, 0, 1000, 2000, ....</LI>
<LI>When working with VHDL unsigned, we tend to write constants using hex notation rather than binary notation - just because it is easier and less prone to error. For example with unsigned(15 downto 0), you have dec(1000) = "0000001111101000" = x"03E8". Many calculators (eg. the one found in MS WIN10) have a "Programmer" setting which makes it easy to convert from decimal to hex notation.</LI>
<LI>If Vivado behavioral simulation shows that our VHDL is working then we usually say GREAT and move on. </LI>
<LI>There is nothing wrong with using MATLAB to further verify things - but (as you say) there is a communication interface to worry about and somehow MATLAB is converting your unsigned numbers to an ADC voltage? In this case, I think your use of MATLAB is not helping with your FPGA work.</LI>
</OL>
<P>Cheers,<BR />Mark</P>Tue, 30 Jun 2020 23:29:24 GMThttps://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1123224#M18151markg@prosensing.com2020-06-30T23:29:24ZRe: Math operations on unsigned (adding)
https://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1125592#M18234
<P><U>As you said, I had a problem with communication.</U></P><P>I was skipping some samples and jumping to the 3rd next sample instead of the next:</P><P>Current sample: #3</P><P>Next Sample: #2 (should be #4 but it goes to #4, then #1, then #2)</P><P>This gave me a wrong illusion.</P>Tue, 07 Jul 2020 15:16:06 GMThttps://forums.xilinx.com/t5/FPGA-Configuration/Math-operations-on-unsigned-adding/m-p/1125592#M18234Mason12020-07-07T15:16:06Z