topic Re: binary multiplication in vhdl in General Technical Discussion
https://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3670#M360
<BR />Hello....<BR /><BR />The problem is that the entity declaration of the vmul8x8i component uses the UNSIGNED type for the ports while the testbench uses std_logic_vector type (this is also noted at the auto-generated testbench) and also that you use the std_logic_arith package.<BR /><BR />The best way is to use everywhere std_logic_vector type and the std_logic_unsigned package. This package contains functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type UNSIGNED. This is also a simple way of allowing data of type STD_LOGIC_VECTOR to participate directly in arithmetic operations.<BR /><BR />Alternatively you can use everywhere the unsigned type.<BR /><BR />Hope that helps....<BR /><BR />George<BR /><BR /><BR />Wed, 05 Dec 2007 18:17:54 GMTgtze2007-12-05T18:17:54Zbinary multiplication in vhdl
https://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3659#M359
<DIV><FONT color="#0000ff">hi, </FONT></DIV>
<DIV><FONT color="#0000ff">I am having problem with simulink, when simulationg a test bench concerning binary multiplication in vhdl.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT color="#ff0000" size="4">the code for the code is this one:</FONT></DIV>
<DIV> </DIV>
<DIV>library IEEE;<BR />use IEEE.std_logic_1164.all;<BR />use IEEE.std_logic_arith.all;<BR />entity vmul8x8i is<BR />port (<BR />X: in UNSIGNED (7 downto 0);<BR />Y: in UNSIGNED (7 downto 0);<BR />P: out UNSIGNED (15 downto 0)<BR />);<BR />end vmul8x8i;<BR />architecture vmul8x8i_arch of vmul8x8i is<BR />begin<BR />P <= X * Y;<BR />end vmul8x8i_arch;</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV><FONT color="#ff3300" size="4">and for the test bench is:</FONT></DIV>
<DIV> </DIV>
<DIV><BR />-- VHDL Test Bench Created from source file vmul8x8i.vhd -- 22:46:03 12/04/2007<BR />--<BR />-- Notes: <BR />-- This testbench has been automatically generated using types std_logic and<BR />-- std_logic_vector for the ports of the unit under test. Xilinx recommends <BR />-- that these types always be used for the top-level I/O of a design in order <BR />-- to guarantee that the testbench will bind correctly to the post-implementation <BR />-- simulation model.<BR />--<BR />LIBRARY ieee;<BR />USE ieee.std_logic_1164.ALL;<BR />USE ieee.numeric_std.ALL;</DIV>
<DIV><BR />ENTITY vmul8x8i_mul_t_vhd_tb IS<BR />END vmul8x8i_mul_t_vhd_tb;</DIV>
<DIV>ARCHITECTURE behavior OF vmul8x8i_mul_t_vhd_tb IS </DIV>
<DIV> COMPONENT vmul8x8i<BR /> PORT(<BR /> X : IN std_logic_vector(7 downto 0);<BR /> Y : IN std_logic_vector(7 downto 0); <BR /> P : OUT std_logic_vector(15 downto 0)<BR /> );<BR /> END COMPONENT;</DIV>
<DIV> SIGNAL X : std_logic_vector(7 downto 0);<BR /> SIGNAL Y : std_logic_vector(7 downto 0);<BR /> SIGNAL P : std_logic_vector(15 downto 0);</DIV>
<DIV>BEGIN</DIV>
<DIV> uut: vmul8x8i PORT MAP(<BR /> X => X,<BR /> Y => Y,<BR /> P => P<BR /> );</DIV>
<DIV><BR />-- *** Test Bench - User Defined Section ***<BR /> tb : PROCESS<BR /> BEGIN</DIV>
<DIV> X <= "00000001";<BR /> Y <= "00000010";<BR /> wait; -- will wait forever<BR /> END PROCESS;<BR />-- *** End Test Bench - User Defined Section ***</DIV>
<DIV>END;<BR /></DIV>
<DIV><FONT color="#ff0000" size="4">and the error reported is:</FONT></DIV>
<DIV> </DIV>
<DIV>types do not match for port X.</DIV>
<DIV> </DIV>
<DIV>can anybody tell me the reason of this.</DIV>
<DIV> </DIV>
<DIV>thanks,</DIV>Wed, 05 Dec 2007 15:09:07 GMThttps://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3659#M359zozulak2007-12-05T15:09:07ZRe: binary multiplication in vhdl
https://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3670#M360
<BR />Hello....<BR /><BR />The problem is that the entity declaration of the vmul8x8i component uses the UNSIGNED type for the ports while the testbench uses std_logic_vector type (this is also noted at the auto-generated testbench) and also that you use the std_logic_arith package.<BR /><BR />The best way is to use everywhere std_logic_vector type and the std_logic_unsigned package. This package contains functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type UNSIGNED. This is also a simple way of allowing data of type STD_LOGIC_VECTOR to participate directly in arithmetic operations.<BR /><BR />Alternatively you can use everywhere the unsigned type.<BR /><BR />Hope that helps....<BR /><BR />George<BR /><BR /><BR />Wed, 05 Dec 2007 18:17:54 GMThttps://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3670#M360gtze2007-12-05T18:17:54ZRe: binary multiplication in vhdl
https://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3674#M361
<DIV>
<DIV>Hi George,</DIV>
<DIV> </DIV>
<DIV>Thanks a lot for the answer. I adopted your solution and now the simulations runs as expected.</DIV>
<DIV> </DIV>
<DIV>Ivan</DIV></DIV>Wed, 05 Dec 2007 19:05:35 GMThttps://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3674#M361zozulak2007-12-05T19:05:35ZRe: binary multiplication in vhdl
https://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3687#M363
Despite the naming, std_logic_arith and std_logic_unsigned aren't actually standard packages. While I won't argue with a working solution, if you ever need to combine the use of signed and unsigned arithmetic in a system, they can lead to problems, so for larger systems I'd recommend sticking to IEEE.numeric_std. Using numeric_std does mean that you'll sometimes need to code explicit type casts between std_logic_vector, unsigned, and signed types, but IMHO that's a fairly small price to pay.<BR /><DIV></DIV>Thu, 06 Dec 2007 01:06:04 GMThttps://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/3687#M363brouhaha2007-12-06T01:06:04ZRe: binary multiplication in vhdl
https://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/421635#M17340
<P>Hi, I need structure model code for 8-bit muliplier using conventional method. Can anyone help me out of this?</P>Sun, 02 Mar 2014 01:38:11 GMThttps://forums.xilinx.com/t5/General-Technical-Discussion/binary-multiplication-in-vhdl/m-p/421635#M17340umeshkumar_19922014-03-02T01:38:11Z