topic problem with multiplication Xilinx spartan in Spartan® Family FPGAs (Archived)
https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/problem-with-multiplication-Xilinx-spartan/m-p/701583#M34541
<P>I have an array of integers with positive and negative values (sine) and when multiplied by 3 there is an error in the sign ((-177 * 3) + 2048 = 2579) when it should be 1517. In the simulation if it works, but in the fpga no. This is a part of the code:</P>
<P> </P>
<P>datos : OUT std_logic_vector(11 downto 0)</P>
<P> </P>
<P>architecture Behavioral of senoYdac is<BR /> type tabla is array (0 to 23) of integer;<BR /> signal calculo: integer ;<BR />begin</P>
<P>process(reloj)</P>
<P> constant seno : tabla := (0,177,341,482,591,659,682,659,591,482,341,177,0,-177,-341,-482,-591,-659,-682,-659,-591,-482,-341,-177);</P>
<P>begin</P>
<P>valorSeno := valorSeno+1;</P>
<P>calculo <= (seno(valorSeno)*3+2048);<BR /> datos <= conv_std_logic_vector(calculo, 12);</P>
<P> </P>
<P>I hope your help!!</P>Mon, 30 May 2016 15:08:38 GMTdavogarcia2016-05-30T15:08:38Zproblem with multiplication Xilinx spartan
https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/problem-with-multiplication-Xilinx-spartan/m-p/701583#M34541
<P>I have an array of integers with positive and negative values (sine) and when multiplied by 3 there is an error in the sign ((-177 * 3) + 2048 = 2579) when it should be 1517. In the simulation if it works, but in the fpga no. This is a part of the code:</P>
<P> </P>
<P>datos : OUT std_logic_vector(11 downto 0)</P>
<P> </P>
<P>architecture Behavioral of senoYdac is<BR /> type tabla is array (0 to 23) of integer;<BR /> signal calculo: integer ;<BR />begin</P>
<P>process(reloj)</P>
<P> constant seno : tabla := (0,177,341,482,591,659,682,659,591,482,341,177,0,-177,-341,-482,-591,-659,-682,-659,-591,-482,-341,-177);</P>
<P>begin</P>
<P>valorSeno := valorSeno+1;</P>
<P>calculo <= (seno(valorSeno)*3+2048);<BR /> datos <= conv_std_logic_vector(calculo, 12);</P>
<P> </P>
<P>I hope your help!!</P>Mon, 30 May 2016 15:08:38 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/problem-with-multiplication-Xilinx-spartan/m-p/701583#M34541davogarcia2016-05-30T15:08:38ZRe: problem with multiplication Xilinx spartan
https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/problem-with-multiplication-Xilinx-spartan/m-p/701604#M34542
<P>When you say it works in simulation, I suppose you mean Behavioral Simulation? Doe it also work in Post-Translate Simulation?</P>
<P> </P>
<P>Which device are you targetting? Spartan 3? Spartan 6?</P>
<P> </P>
<P>If this is Spartan 3, then possibly you should try to use the "new parser" to see if that changes the behavior.</P>Mon, 30 May 2016 18:53:45 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/problem-with-multiplication-Xilinx-spartan/m-p/701604#M34542gszakacs2016-05-30T18:53:45ZRe: problem with multiplication Xilinx spartan
https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/problem-with-multiplication-Xilinx-spartan/m-p/701696#M34546
<P>I think you have more issues that the one you mention because a 12-bit signed value can only cover the range -2048 to + 2047. Therefore, the addition of 2048 to any of your positive values doesn’t really work; it may just appear to work because adding 2048 is changing the sign (MSB) of a 12-bit representation whilst leaving the lower 11 bits the same.</P>
<P> </P>
<P>For example, ((659 * 3) + 2048) = +4025. This is FB9 hex but in a 12-bit signed system that means -71. However, (659 * 3) = +1977 which is 7B9 hex which has exactly the same lower 11-bits.</P>
<P> </P>
<P>The following answer record relating to ‘conv_std_logic_vector’ may also be useful.</P>
<P> </P>
<P><A href="http://www.xilinx.com/support/answers/4644.html" target="_blank">http://www.xilinx.com/support/answers/4644.html</A></P>
<P> </P>Tue, 31 May 2016 10:58:58 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/problem-with-multiplication-Xilinx-spartan/m-p/701696#M34546chapman2016-05-31T10:58:58Z