topic Re: I need to implement a arithmetic,but the timing is not met, how can I fix it? in Timing Analysis
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728408#M10464
<P>If I add a register before <SPAN>Cmult1, then the formula is not right, I think.</SPAN></P>
<P> </P>
<P><SPAN>I have uploaded my .slx file before, can you please take a look at it? Thanks very much.</SPAN></P>Fri, 14 Oct 2016 14:24:26 GMTretni2016-10-14T14:24:26ZI need to implement a arithmetic,but the timing is not met, how can I fix it?
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728398#M10460
<P>The arithmetic is:</P>
<P> </P>
<P>s[n] = s[n-1]*(1-c) + din[n]*c</P>
<P> </P>
<P>And I need it run in 200MHz, but the timing report showed it was not met the timing.</P>
<P> </P>
<P>My sysgen project is this</P>
<P> </P>
<P>How can I improve the timing?</P>Fri, 14 Oct 2016 13:26:57 GMThttps://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728398#M10460retni2016-10-14T13:26:57ZRe: I need to implement a arithmetic,but the timing is not met, how can I fix it?
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728402#M10461
<P>HI <LI-USER uid="18819"></LI-USER></P>
<P><BR />Are you facing setup violations? <BR />If the violations are internal to addsub module,</P>
<P>How are you implementing the Addsub module? using Fabric or DSP48?<BR />Double click on the Addsub, in the implementation tab , check the pipeline for maximum performance option.<BR /><BR />share your slx file here if possible.<BR /><BR /><BR /></P>Fri, 14 Oct 2016 13:41:10 GMThttps://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728402#M10461nagabhar2016-10-14T13:41:10ZRe: I need to implement a arithmetic,but the timing is not met, how can I fix it?
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728404#M10462
<P>That's a combinatorial loop. In any case, it's not correct to your equation. You need a register in your feedback path before Cmult1. That should solve both problems.</P>Fri, 14 Oct 2016 13:57:20 GMThttps://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728404#M10462bwiec2016-10-14T13:57:20ZRe: I need to implement a arithmetic,but the timing is not met, how can I fix it?
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728407#M10463
<P>I have tried the <SPAN>Fabric and DSP48 option, but could not meet the timing neither.</SPAN></P>
<P>this is my slx</P>
<P> </P>
<P>thanks~</P>Fri, 14 Oct 2016 14:19:54 GMThttps://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728407#M10463retni2016-10-14T14:19:54ZRe: I need to implement a arithmetic,but the timing is not met, how can I fix it?
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728408#M10464
<P>If I add a register before <SPAN>Cmult1, then the formula is not right, I think.</SPAN></P>
<P> </P>
<P><SPAN>I have uploaded my .slx file before, can you please take a look at it? Thanks very much.</SPAN></P>Fri, 14 Oct 2016 14:24:26 GMThttps://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728408#M10464retni2016-10-14T14:24:26ZRe: I need to implement a arithmetic,but the timing is not met, how can I fix it?
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728425#M10465
<P>Hello,</P>
<P> </P>
<PRE>s[n] = <STRONG>s[n-1]</STRONG>*(1-c) + din[n]*c
</PRE>
<P>This means the current output sample is dependent on the <EM>previous</EM> output sample. So you need to store the previous output sample in a register and that feeds the mult and finally the adder. The way you have it now, the <EM>current </EM>output sample is feeding the mult/adder.</P>Fri, 14 Oct 2016 15:43:47 GMThttps://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728425#M10465bwiec2016-10-14T15:43:47ZRe: I need to implement a arithmetic,but the timing is not met, how can I fix it?
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728460#M10467
<P>The CMult1 has 1 clock delay itself. So I can not add register which will add another delay.</P>
<P> </P>Sat, 15 Oct 2016 01:42:36 GMThttps://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728460#M10467retni2016-10-15T01:42:36ZRe: I need to implement a arithmetic,but the timing is not met, how can I fix it?
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728521#M10472
<P>What you have run into is a problem with Infinite Impulse Response (IIR) filters. This is why FIR filters are more typically used in an FPGA: even though they are more complex to implement, they can easily be pipelined since they don't depend on the most recent output of the filter, only on the last N inputs to the filter. You may be able to pipeline the IIR filter, however it becomes more complex. For example, you could re-define the equation to use the output from two cycles earlier as well as the most recent two samples. Depending on the logic used to implement the filter, this may or may not help you to meet timing, since it adds more layers of logic as well as adding an additional pipeline stage.</P>Sun, 16 Oct 2016 17:14:47 GMThttps://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728521#M10472gszakacs2016-10-16T17:14:47ZRe: I need to implement a arithmetic,but the timing is not met, how can I fix it?
https://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728535#M10477
<P>Thanks very much.</P>
<P> </P>
<P>I use this equation to generate an adaptive threshold.</P>
<P> </P>
<P>I think I can only run this algorithm on 100MHz on the zedboard....</P>Mon, 17 Oct 2016 01:00:48 GMThttps://forums.xilinx.com/t5/Timing-Analysis/I-need-to-implement-a-arithmetic-but-the-timing-is-not-met-how/m-p/728535#M10477retni2016-10-17T01:00:48Z