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Explorer
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287 次查看
注册日期: ‎02-13-2019

pcie dam/bridge ipcore DMA操作怎么通知CPU操作完成

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在使用PCIE的core实现DMA操作的时候,CPU是怎么知道当前DMA操作有没有结束的?

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Xilinx Employee
Xilinx Employee
234 次查看
注册日期: ‎08-02-2007

回复: pcie dam/bridge ipcore DMA操作怎么通知CPU操作完成

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PCIE 无特定中断管脚 用的是传统消息中断或者msix msi 具体需要看IP core 和CPU 配置

poll mode 的写回地址是有特殊寄存器定义的 ,原文如下

The writeback address is defined by the Pollmode_hi_wb_addr and Pollmode_lo_wb_addr registers (see Table 2-48 and Table 2-49 for H2C, and Table 2-67 and Table 2-68 for C2H).

具体需要看pg195

 

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Xilinx Employee
Xilinx Employee
246 次查看
注册日期: ‎08-02-2007

回复: pcie dam/bridge ipcore DMA操作怎么通知CPU操作完成

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默认情况下 当dma 请求完成时 dma engine 会发出中断告诉cpu 

如果改变默认设置 用poll mode 那么DMA engine 会在完成dma 后 往CPU 的memory 写特定的数告诉CPU 已经完成

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Explorer
Explorer
242 次查看
注册日期: ‎02-13-2019

回复: pcie dam/bridge ipcore DMA操作怎么通知CPU操作完成

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@liy 如果是中断方式,是有专门的中断管脚还是通过PCIE总线写中断寄存器通知CPU?

poll mode下,memory中写特定数据,这个特定数据是什么,写在什么位置啊?哪里能够查到呢?
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Xilinx Employee
Xilinx Employee
235 次查看
注册日期: ‎08-02-2007

回复: pcie dam/bridge ipcore DMA操作怎么通知CPU操作完成

转到解答

PCIE 无特定中断管脚 用的是传统消息中断或者msix msi 具体需要看IP core 和CPU 配置

poll mode 的写回地址是有特殊寄存器定义的 ,原文如下

The writeback address is defined by the Pollmode_hi_wb_addr and Pollmode_lo_wb_addr registers (see Table 2-48 and Table 2-49 for H2C, and Table 2-67 and Table 2-68 for C2H).

具体需要看pg195

 

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Explorer
Explorer
221 次查看
注册日期: ‎02-13-2019

回复: pcie dam/bridge ipcore DMA操作怎么通知CPU操作完成

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@liy 消息中断或者 msi的中断处理,cpu是怎么知晓有这些中断的,流程是怎么样的呢?
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Xilinx Employee
Xilinx Employee
185 次查看
注册日期: ‎08-02-2007

回复: pcie dam/bridge ipcore DMA操作怎么通知CPU操作完成

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这些都是驱动实现的 驱动需要查询设备是否支持中断 如果支持 则需要配置中断寄存器 

这些在libxdma.c 文件里面有具体代码

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