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关于Timing Analysis 的问题

发帖数: 6
注册日期: ‎01-21-2018

关于Timing Analysis 的问题


我今天看了 Analyzing Input Timing,如下面的 链接所讲:




看了之后,不是很懂,列出了两个问题,如下面的 图片所示,烦请 大牛们 赐教,谢谢!



Xilinx Employee
发帖数: 1,250
注册日期: ‎07-17-2008

回复: 关于Timing Analysis 的问题

1. slack旁边的等式就是计算公式: requirement - (data path - clock path - clock arrival + uncertainty)



2. 第一列为location,也就是路径所经由的物理实体;第二列为delay type,也就是延时类型,是器件的逻辑延时还是布线延时,或者是同步器件的建立/保持时间;第三列为Delay值,列出每一项对应的具体延时值。

以此路径为例,data path是从输入管脚一直到寄存器。D13.I为起点,表示管脚D13输入口;SLICE_X27Y52.BX为寄存器所在SLICE的数据输入口;SLICE_X27Y52.CLK为寄存器的时钟输入口。


e.g. C:\Xilinx\14.7\ISE_DS\ISE\doc\usenglish\help\delay_types\html\web_ds

Tiopi可查看ta_tiopi图示及描述,表示从管脚封装到input buffer输出的延时


Don't forget to reply, kudo, and accept as solution.
发帖数: 444
注册日期: ‎01-22-2015

回复: 关于Timing Analysis 的问题

( 大牛们 ) Big cow says…


You are seeing only the tail of the elephant and trying to understand the whole elephant. I am sorry to say that the old ISE software has very little documentation that will help you. However, Xilinx has created the Vivado software to replace ISE. Vivado documents will help answer your questions.


First, please note that your questions are from ISE document about “Input Timing”.   Input Timing is used to analyze “Source Synchronous Input” to the FPGA. Source Synchronous Input means that a device outside the FPGA is sending a clock and data to the FPGA.


First, I suggest you study basics of Timing Analysis found in Chapter 5 of Xilinx document UG906.   Then, I suggest you read about Constraining I/O Delay in Chapter 4 of Xilinx document UG903.   Please note that UG906 and UG903 are documents for the Vivado software. However, concepts of “Timing Analysis” and “Constraining I/O Delay” are similar for Vivado and ISE.