06-12-2018 10:49 AM - 编辑日期 06-12-2018 11:01 AM
(English version of this problem is at the 2nd floor)
ISim P.20131013 (signature 0xfbc00daa) This is a Full version of ISim. Time resolution is 1 ps Simulator is doing circuit initialization process. Block Memory Generator CORE Generator module loading initial data... WARNING: at 0 ps: file Mem.mif could not be opened 1465331350153982224147467232072913762988861607380484459110551152183111192004746149403861397757651932798722481622905633130827289426003030588447311599813222195 21785092811483494 Stopped at time : 0 fs : File "/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v" Line 50
修改时间 06-12-2018 10:56 AM
English version of the problem:
I am using ISE14.7 to write verilog and my current environment is ubuntu 18.04.
I generate an IP core and give it a .coe file as it's initialization.
During the generating process, we can preview the file content of this .coe file. And I think that it means this .coe is loaded successfully.
But ISE still went wrong when simulating, it has the following log:
I have looked up in the internet that .mif format is generated automatically from .coe file by ISE. However I still have no idea about the weird error.
Thank you very much!
修改时间 06-12-2018 12:24 PM
Where do you do simulation ?
If you know the working directory, you should copy .coe file into working directory.
It's a working directory issue.
If you use Vivado, you can set loadable directories.