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wwlcumt
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注册日期: ‎07-25-2020

PUDC_B can alternatively be tied High setting the non-dedicated configuration I/Os to 3-state during configuration

ug470 page66 里有以下这句话

The FPGA PUDC_B pin is tied to ground in this sample schematic enabling internal pull-ups during configuration, including the non-dedicated configuration I/Os.
PUDC_B can alternatively be tied High setting the non-dedicated configuration I/Os to 3-state during configuration.

请问这句话说明在配置期间,

1)PUDC_B 接地的话,普通IO电平是高电平吗?,还是低电平,还是高阻?

2)PUDC_B 接3.3V的话,普通IO电平是高电平吗,低电平,还是高阻?

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shengjie
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注册日期: ‎07-01-2019

PUDC_B接地,IO内部上拉到VCCO,是高电平

PUDC_B拉高,IO内部无上拉,是三态状态,也就是高阻态

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