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DSP48E2 布局时出错

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发帖数: 3
注册日期: ‎07-11-2018
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DSP48E2 布局时出错

使用vivado2017.4版本工具,在综合代码时,代码的实现方式为E= A*B + C*D;工具调用了DSP48E来实现,报出了如下错误提示:

ERROR : when use  DSP48E2 AREG attribute is set to 2, the CEA1 and CEA2 inpout pins cannot be unconneted or tied to GND.

麻烦大侠们指点迷津,不胜感激。。。

Error 截图.jpg

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Moderator
发帖数: 465
注册日期: ‎11-05-2010

Re: DSP48E2 布局时出错

Hi @shunzhang114114
这种情况需要先在网表中断开原来的接地(disconnect_net命令),然后再把目标pin拉高.
Example:
disconnect_net -net XX -objects [get_pins XX/CEA1]
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

在原帖中查看解决方案


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Xilinx Employee
发帖数: 158
注册日期: ‎08-26-2010

Re: DSP48E2 布局时出错

Hi @shunzhang114114,

 

AREG=2,A会用2个pipe line reg,需要这两个时钟使能设置为1来使能。

 

Thanks

Simon

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Don't forget to reply, kudo, and accept as solution.
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Visitor
发帖数: 3
注册日期: ‎07-11-2018

Re: DSP48E2 布局时出错

感谢您的解答和指导。

这两个时钟时能设置为1,需要怎么来设置? 有没有对应的tcl命令,或者是修改DSP48E2的宏定义,需要怎么设置?

麻烦您抽空指导,谢谢。

Xilinx Employee
发帖数: 158
注册日期: ‎08-26-2010

Re: DSP48E2 布局时出错

Hi @shunzhang114114

 

DSP48E2的这两个端口置1就可以了。

 

// Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
.CEA1(CEA1), // 1-bit input: Clock enable input for 1st stage AREG
.CEA2(CEA2), // 1-bit input: Clock enable input for 2nd stage AREG

 

Thanks

Simon

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Moderator
发帖数: 465
注册日期: ‎11-05-2010

Re: DSP48E2 布局时出错

Hi @shunzhang114114
DSP48E2 如果是工具推导得到,而不是代码直接例化DSP48E2, 就无法在代码中修改CEA1 pin 的值,需要用命令直接改网表.
你先看一下综合的网表,看下CEA1 pin 是未连接状态还是接地(GND)?
如果是未连接状态,直接使用以下命令拉高.
set_logic_one [get_pins DSP_XX_inst/CEA1]
set_logic_one [get_pins DSP_XX_inst/CEA2]
PS: Pin 的所在的Cell名称改成你自己的
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Visitor
发帖数: 3
注册日期: ‎07-11-2018

Re: DSP48E2 布局时出错

从综合的网表来看,CEA1已经是接地(GND),这种情况下,也是用该命令直接拉高? 或者是需要在网表中断开原来的接地?
Moderator
发帖数: 465
注册日期: ‎11-05-2010

Re: DSP48E2 布局时出错

Hi @shunzhang114114
这种情况需要先在网表中断开原来的接地(disconnect_net命令),然后再把目标pin拉高.
Example:
disconnect_net -net XX -objects [get_pins XX/CEA1]
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------