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注册日期: ‎05-21-2020

The TMR manager IP register state

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I set the TMR register CFIR as 0x00000001, but I read the register from FFR the value is zero, the register state is not correct for me.

And the basic setting for the IP as followed:

40ABB46D.PNG5140978A.PNGD0A6F71C.PNG

 

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Xilinx Employee
Xilinx Employee
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注册日期: ‎06-19-2019

回复: The TMR manager IP register state

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There are two ways to inject faults with the TMR solution:
  1. Instruction fault injection with the TMR Inject IP core. In that case, an instruction is modified for one of the processors to cause a discrepancy between them.
  2. Inserting faults in the TMR comparators to flip one particular bit of the comparison. In this case you enable fault injection with the CFIR register, but you also have to input the bits to be flipped via the TMR comparator AXI4-Stream interfaces. This can be done from outside the TMR subsystem, or from the TMR processors if you connect the TMR comparators to MicroBlaze AXI-Stream interfaces.
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Xilinx Employee
Xilinx Employee
113 次查看
注册日期: ‎06-19-2019

回复: The TMR manager IP register state

跳至解决方案
There are two ways to inject faults with the TMR solution:
  1. Instruction fault injection with the TMR Inject IP core. In that case, an instruction is modified for one of the processors to cause a discrepancy between them.
  2. Inserting faults in the TMR comparators to flip one particular bit of the comparison. In this case you enable fault injection with the CFIR register, but you also have to input the bits to be flipped via the TMR comparator AXI4-Stream interfaces. This can be done from outside the TMR subsystem, or from the TMR processors if you connect the TMR comparators to MicroBlaze AXI-Stream interfaces.
------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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