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Visitor
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注册日期: ‎01-20-2020

vivado fft 计算结果是不是有问题?

大家好,我用xfft ip核对向量[1,2,3,4,5,6,7,8,0,0,0,0,0,0,0,0]进行FFT,计算结果序列的第一个数据为34(X"22")。这明显不对,正确的FFT计算结果序列的第一个数据应该是36。为什么ip核会计算出不正确的结果?谢谢大家~

 

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2020/02/10 17:35:14
-- Design Name:
-- Module Name: sim_fft_ifft - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sim_fft_ifft is
-- Port ( );
end sim_fft_ifft;

architecture Behavioral of sim_fft_ifft is
COMPONENT fft_0
PORT (
aclk : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(79 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_frame_started : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_data_in_channel_halt : OUT STD_LOGIC
);
END COMPONENT;

COMPONENT ifft
PORT (
aclk : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(79 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_frame_started : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC;
event_data_in_channel_halt : OUT STD_LOGIC
);
END COMPONENT;

signal s_axis_config_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := X"01";
signal s_axis_config_tvalid : STD_LOGIC := '0';
signal s_axis_config_tready : STD_LOGIC;
signal s_axis_data_tdata : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0');
signal s_axis_data_tvalid : STD_LOGIC := '0';
signal s_axis_data_tlast : STD_LOGIC := '0';
signal s_axis_data_tready : STD_LOGIC;
signal m_axis_data_tdata : STD_LOGIC_VECTOR(79 DOWNTO 0) := (others => '0');
signal m_axis_data_tvalid : STD_LOGIC;
signal m_axis_data_tlast : STD_LOGIC;

signal si_axis_config_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
signal si_axis_config_tvalid : STD_LOGIC := '0';
signal si_axis_config_tready : STD_LOGIC;
signal si_axis_data_tdata : STD_LOGIC_VECTOR(63 DOWNTO 0) := (others => '0');
signal si_axis_data_tvalid : STD_LOGIC := '0';
signal si_axis_data_tlast : STD_LOGIC := '0';
signal si_axis_data_tready : STD_LOGIC;
signal mi_axis_data_tdata : STD_LOGIC_VECTOR(79 DOWNTO 0) := (others => '0');
signal mi_axis_data_tvalid : STD_LOGIC;
signal mi_axis_data_tlast : STD_LOGIC;

constant PERIOD : time := 10ns;
signal aclk : STD_LOGIC := '0';
signal num : std_logic_vector(15 downto 0) := (others => '0');
begin
U1 : fft_0 PORT map(
aclk => aclk,
s_axis_config_tdata => s_axis_config_tdata,
s_axis_config_tvalid => s_axis_config_tvalid,
s_axis_config_tready => s_axis_config_tready,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tlast => s_axis_data_tlast,
s_axis_data_tready => s_axis_data_tready,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tlast => m_axis_data_tlast
);

U2 : ifft PORT map(
aclk => aclk,
s_axis_config_tdata => si_axis_config_tdata,
s_axis_config_tvalid => si_axis_config_tvalid,
s_axis_config_tready => si_axis_config_tready,
s_axis_data_tdata => si_axis_data_tdata,
s_axis_data_tvalid => si_axis_data_tvalid,
s_axis_data_tlast => si_axis_data_tlast,
s_axis_data_tready => si_axis_data_tready,
m_axis_data_tdata => mi_axis_data_tdata,
m_axis_data_tvalid => mi_axis_data_tvalid,
m_axis_data_tlast => mi_axis_data_tlast
);

aclk <= not aclk after PERIOD/2;

process
begin
wait until rising_edge(aclk);
if(num < X"2000") then
num <= num + 1;
else
num <= num;
end if;
end process;

process
begin
wait until rising_edge(aclk);
if(num > X"0002" and num < X"0005") then
s_axis_config_tvalid <= '1';
si_axis_config_tvalid <= '1';
else
s_axis_config_tvalid <= '0';
si_axis_config_tvalid <= '0';
end if;
end process;

process
begin
wait until rising_edge(aclk);
if(num > X"0008" and num <= X"0018") then
s_axis_data_tvalid <= '1';
si_axis_data_tvalid <= '1';
else
s_axis_data_tvalid <= '0';
si_axis_data_tvalid <= '0';
end if;
end process;

process
begin
wait until rising_edge(aclk);
if(num > X"0008" and num <= X"0010") then
s_axis_data_tdata <= s_axis_data_tdata + X"10";
si_axis_data_tdata <= si_axis_data_tdata + X"10";
else
s_axis_data_tdata <= (others => '0');
si_axis_data_tdata <= (others => '0');
end if;
end process;

process
begin
wait until rising_edge(aclk);
if(num = X"0018") then
s_axis_data_tlast <= '1';
si_axis_data_tlast <= '1';
else
s_axis_data_tlast <= '0';
si_axis_data_tlast <= '0';
end if;
end process;


end Behavioral;

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Highlighted
Moderator
Moderator
246 次查看
注册日期: ‎08-02-2007

回复: vivado fft 计算结果是不是有问题?

你做了scaling? 检查一下有没有做scaling, 另外你是怎么得到预期结果值的? 自己算的? Matlab FFT算的? 

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Visitor
Visitor
198 次查看
注册日期: ‎01-20-2020

回复: vivado fft 计算结果是不是有问题?

我设置的是unscaled。至于那个预期结果值是根据傅里叶变换公式算的啊,结果序列第一个值就是原始序列全部项的累加和啊

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Moderator
Moderator
137 次查看
注册日期: ‎08-02-2007

回复: vivado fft 计算结果是不是有问题?

1. 傅里叶公式计算的是理论值, 实际上的值由于精度关系肯定是有偏差, FFT IP涉及到就是input data width和phase width, input data width应该没有问题, 因为你的输入数据都是整数, 可以增加phase width.

2. 确保FFT IP功能的正确, 这个IP功能是没问题的, 有确保的是FFT IP input timing, 这点这个IP已经提供了demo test bench, 按照demo test bench仿真的input timing仔细对照你的仿真图, 或者直接在demo test bench改成你需要的数据. Demo test bench见PG109 chapter 6 - test bench.

 

Please accept as solution if it answers your question.

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Voyager
Voyager
121 次查看
注册日期: ‎05-29-2018

回复: vivado fft 计算结果是不是有问题?

你用IP将输出的结果做IFFT看能不能得到原始数据就知道了,当然IP配置要正确。
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