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DDR3 write latency calibration error

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发帖数: 1
注册日期: ‎05-11-2018

DDR3 write latency calibration error

Hi, Sir

     I am using XCKU060 in my project,  and debug  DDR3 with software reset,  found  error  for write latency calibration sometime,  the error message is :

       "Could not find data pattern with the allocated number of taps  Error found on Rank 1, Byte 5."

        This problem was not found ,  Please tell me how to resolve this bug.

 

   Thanks

    Jason 

 

  2018-5-14

      

     

Xilinx Employee
发帖数: 182
注册日期: ‎08-21-2007

回复: DDR3 write latency calibration error

Was the calibration failure also found in this stage? Did you try on the lower data rate? Was the problem reproduced on one or several boards?