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Adventurer
Adventurer
73 次查看
注册日期: ‎02-15-2019

基于ZCU106开发板更换UART0端口后

基于ZCU106开发板更换了uart0的端口为MIO22、MIO23,在SDK中生成了FSBL,在petalinux中生成了u-boot,fsbl和u-boot已经加载成功,同时把内核加载到指定的区域。在JTAG、SPI启动模式都运行卡在图下的位置,担心没加载bitstream,在JTAG模式单独加载了bitstream。

[    0.000003] sched_clock: 56 bits at 99MHz, resolution 10ns, wraps every 4398046511101ns
[    0.008243] Console: colour dummy device 80x25
[    0.012377] console [tty0] enabled
[    0.015744] bootconsole [cdns0] disabled

UART0的在zcu106-reva.dtsi的pinctl已经改为如下配置:

	pinctrl_uart0_default: uart0-default {
		mux {
			groups = "uart0_4_grp";
			function = "uart0";
		};

		conf {
			groups = "uart0_4_grp";
			slew-rate = <1>;
			io-standard = <1>;
		};

		conf-rx {
			pins = "MIO22";
			bias-high-impedance;
		};

		conf-tx {
			pins = "MIO23";
			bias-disable;
		};
	};

请问有什么办法能够判别到底是什么原因卡在这里了吗?

还有,如果是串口问题,能不能在kernel启动后继续使用FSBL、U-BOOT阶段的串口进行输出?

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Xilinx Employee
Xilinx Employee
31 次查看
注册日期: ‎09-14-2018

回复: 基于ZCU106开发板更换UART0端口后

hi @liufengwuhen 

可以上传完整的boot log吗?

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