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Participant jt779862810
Participant
212 次查看
注册日期: ‎09-12-2018

AXI Interconnect decode error

Block Design在使用AXI Interconnect IP 的时候,将AXI Interconnect配置成两个slave端一个master端,S00接用户逻辑,S01接用户逻辑,M00接MIG IP。

在仿真的时候S00 和 S01 的BRESP 返回值为3,根据协议判断是decode error,一般典型使用在内部互联结构,指示发送地址没有slave。内部AXI Crossbar 解码错误。请问该怎么解决?是哪里出了问题?

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2 条回复2
Xilinx Employee
Xilinx Employee
175 次查看
注册日期: ‎09-01-2014

回复: AXI Interconnect decode error

DECERR一般是由未定义地址引起的, 请确认一下S00或S01的Master发送的地址是否在Address Editor的定义范围内
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Xilinx Employee
Xilinx Employee
163 次查看
注册日期: ‎03-27-2013

回复: AXI Interconnect decode error

根据AXI协议:Decode error. Generated, typically by an interconnect component, to indicate that there is no slave at the transaction address

BRESP回这个的话建议优先查看下相关的AXI写操作是否提供了正确的地址。

另外,你的波形中好像无法看到AW通道的握手,无法看到具体使用什么地址访问的。

Best Regards,
Jason
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