修改时间 02-13-2019 02:39 PM
now i instantiated AXI interconnect in my design, first i write data to slave model, then read the same address of slave model immediately , at this time , write data still in AXI interconnect, not yet transimit to slave model,
my problem is how to ensure that i can read new write data from slave model? i should wait for write reaponse then read? or i can read after write, and configure some parameter, axi fabric internal can handle this case, read data from internal fifo?
修改时间 02-14-2019 01:14 PM
I setup a test with axiconnect, but I cannot regerate your problem.
I wrote to a PL register and read back immediatly, and alway get the just-written value.
1. How do you judge that write data is still in interconnect in your design?
2. Could you share us your test process and code, so we can take a deeper look into your problem.
Don't forget to kudo and accept as solution.
修改时间 02-15-2019 10:43 AM
Thanks for your replay
in my simulation environment, there is a master model connect to AXI interconnect SI,a slave model connect to AXI interconnect MI, since write data transfer from master to salve need through AXI interconnect，its internal have much subset ip, like CDC, data width converter, crossbar and so on, so write data from master to slave have probably 80ns delay, but read command from master to slave need only 60 ns probably, that is to say , salve model first get read command, then get write data, maybe slave model should wait for write data finshed then transmit just-written value as read data?