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Visitor fpga_boy
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248 次查看
注册日期: ‎06-04-2019

vivado生成bit文件时内存冲突报错

批注 2019-11-20 105918.png

vivado中的BD文件如上,在生成bit文件时会报错,

[BD 41-971] Segment </processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM> mapped into </Conv_0/Data_m_axi_gmem> at 0x00000000[ 1G ] overlaps with </processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM> mapped at 0x00000000[ 1G ]

批注 2019-11-20 110241.png批注 2019-11-20 110258.png应该怎么解决这个错误?

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Xilinx Employee
Xilinx Employee
174 次查看
注册日期: ‎06-19-2019

回复: vivado生成bit文件时内存冲突报错

从你报错信息来看,是2个地址冲突了,修改其中一个的offset和high address就可以了。

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Visitor fpga_boy
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140 次查看
注册日期: ‎06-04-2019

回复: vivado生成bit文件时内存冲突报错

您好,这个问题已经解决了,但是还是不能生成bit文件,错误是[DRC INBB-3] Black Box Instances: Cell 'design_1_i/Conv_0/inst/Conv_fadd_32ns_32ns_32_5_full_dsp_U0/Conv_ap_fadd_3_full_dsp_32_u/U0' of type 'floating_point_v7_1_2' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.请问这是什么原因?这个IP是我用hls生成的也没报错啊微信截图_20191121160857.png

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Xilinx Employee
Xilinx Employee
90 次查看
注册日期: ‎06-19-2019

回复: vivado生成bit文件时内存冲突报错

从你信息上看,是上面design的critical warning导致的。

在source界面下的工程下,按照提示的路径检查是否包含了floating_point_v7_1_2这个IP

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