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Xilinx Employee
Xilinx Employee
59 次查看
注册日期: ‎02-16-2012

【分享】 MPSoC的GEM通过SGMII直接和其它CPU、switch芯片连接


MPSoC的GEM可以通过SGMII直接和其它CPU、switch芯片连接。这种情况,外部没有phy设备,不能自协商,需要设置成固定速率。
MPSoC和对端都必须设置成一样速率,通常设置为1000MHz。

Device tree如下设置:

&gem3 {
phy-mode = "sgmii";
is-internal-pcspma = <0x1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};

在uboot的zynq_gem.c里添加下列函数zynq_gem_check(),在zynq_gem_init返回前调用zynq_gem_check(), zynq_gem_send()和zynq_gem_recv()里调用zynq_gem_check(),检查寄存器。LOG_INFO可以替换成printf.
SGMII Link要正常,也就是寄存器里的pcs_link_state,才能工作。

static int zynq_gem_check(struct udevice *dev)
{
u32 *p_u32;
u32 u32_value;
u32 nwctrl;
u32 nwconfig;
u32 nwsr;
u32 txsr;
u32 rxsr;
u32 pcscntrl;
u32 pcsstatus;
int ret;
struct zynq_gem_priv *priv = dev_get_priv(dev);
struct zynq_gem_regs *regs = priv->iobase;

LOG_INFO("begin\n");

nwctrl = readl(&regs->nwctrl);
LOG_INFO("nwctrl address: %x, value: %d\n", &regs->nwctrl, nwctrl );


nwconfig = readl(&regs->nwcfg);
LOG_INFO("nwconfig address: %x, value: %d\n", &regs->nwcfg, nwconfig );
if( 0 != ( nwconfig & (1<<27) ) )
{
LOG_INFO("SGMII is enabled in nwconfig.\n" );
}
if( 0 != ( nwconfig & (1<<11) ) )
{
LOG_INFO("pcs_select TBI is enabled in nwconfig.\n" );
}

nwsr = readl(&regs->nwsr);
LOG_INFO("nwconfig address: %x, value: %d\n", &regs->nwsr, nwsr );
if( 0 != ( nwsr & (1<<0) ) )
{
LOG_INFO("pcs_link_state is OK in network_status.\n" );
}

pcscntrl = readl(&regs->pcscntrl);
LOG_INFO("pcscntrl address: %x, value: %d\n", &regs->pcscntrl, pcscntrl );
if( 0 == ( pcscntrl & (1<<15) ) )
{
LOG_INFO("pcscntrl pcs_software_reset is cleared.\n" );
}
if( 0 == ( pcscntrl & (1<<12) ) )
{
LOG_INFO("pcscntrl auto-negotiation is enabled.\n" );
}

pcsstatus = readl(&regs->pcsstatus);
LOG_INFO("pcsstatus address: %x, value: %d\n", &regs->pcsstatus, pcsstatus );
if( 0 == ( pcsstatus & (1<<5) ) )
{
LOG_INFO("pcsstatus Auto-negotiation is completed.\n" );
}
if( 0 == ( pcsstatus & (1<<4) ) )
{
LOG_INFO("pcsstatus remote_fault is set.\n" );
}
if( 0 == ( pcsstatus & (1<<3) ) )
{
LOG_INFO("pcsstatus Auto-negotiation is enabled.\n" );
}
if( 0 == ( pcsstatus & (1<<2) ) )
{
LOG_INFO("pcsstatus link is up.\n" );
}

txsr = readl(&regs->txsr);
LOG_INFO("pcsstatus address: %x, value: %d\n", &regs->txsr, txsr );
if( 0 == ( txsr & (1<<5) ) )
{
LOG_INFO("pcsstatus Auto-negotiation is completed.\n" );
}

rxsr = readl(&regs->rxsr);
LOG_INFO("pcsstatus address: %x, value: %d\n", &regs->rxsr, rxsr );
if( 0 == ( rxsr & (1<<5) ) )
{
LOG_INFO("pcsstatus Auto-negotiation is completed.\n" );
}

// ICM_CFG1 (SERDES) Register Description
p_u32 = (u32 *)0xFD410014 ;
u32_value = readl(p_u32);
LOG_INFO("ICM_CFG1 address: %p, value: %d\n", p_u32, u32_value );
if( 0x5 == ( pcsstatus & (0x7<<4) ) )
{
LOG_INFO("ICM_CFG1 GTR Lane 3 is used as SGMII.\n" );
}

// frames_txed_ok
p_u32 = (u32 *)0xFF0E0108;
u32_value = readl(p_u32);
LOG_INFO("frames_txed_ok address: %p, value: %d\n", p_u32, u32_value );


// broadcast_txed
p_u32 = (u32 *)0xFF0E010C;
u32_value = readl(p_u32);
LOG_INFO("broadcast_txed address: %p, value: %d\n", p_u32, u32_value );


// frames_rxed_ok
p_u32 = (u32 *)0xFF0E0158;
u32_value = readl(p_u32);
LOG_INFO("frames_rxed_ok address: %p, value: %d\n", p_u32, u32_value );


// broadcast_rxed
p_u32 = (u32 *)0xFF0E015C;
u32_value = readl(p_u32);
LOG_INFO("broadcast_rxed address: %p, value: %d\n", p_u32, u32_value );

return 0;
}

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