我这有一个用vivado2015.4建立的工程，我想把它移植到2018.2版本下。
首先通过source TCL 文件，在2015.4版本下恢复了工程，并且编译通过，可以生成比特流；
然后用2018.2版本的vivado打开该工程，完成对IP的upgrade，添加IP路径和xdc文件；
尝试生成比特流文件，出现报错，信息如下：
似乎是与xdc文件有关。贴出xdc中相关的几行
163 set_property MARK_DEBUG true [get_nets design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_wready] 164 set_property MARK_DEBUG true [get_nets design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_awvalid] 165 set_property MARK_DEBUG true [get_nets design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_awready] 166 set_property MARK_DEBUG true [get_nets design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_wvalid] 167 set_property MARK_DEBUG true [get_nets design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/wnext] 168 set_property MARK_DEBUG true [get_nets design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_wlast]
214 connect_debug_port u_ila_0/probe8 [get_nets [list design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_awready]] 215 create_debug_port u_ila_0 probe 216 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9] 217 set_property port_width 1 [get_debug_ports u_ila_0/probe9] 218 connect_debug_port u_ila_0/probe9 [get_nets [list design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_awvalid]] 219 create_debug_port u_ila_0 probe 220 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10] 221 set_property port_width 1 [get_debug_ports u_ila_0/probe10] 222 connect_debug_port u_ila_0/probe10 [get_nets [list design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_wlast]] 223 create_debug_port u_ila_0 probe 224 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11] 225 set_property port_width 1 [get_debug_ports u_ila_0/probe11] 226 connect_debug_port u_ila_0/probe11 [get_nets [list design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_wready]] 227 create_debug_port u_ila_0 probe 228 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12] 229 set_property port_width 1 [get_debug_ports u_ila_0/probe12] 230 connect_debug_port u_ila_0/probe12 [get_nets [list design_1_i/axi_master_ip_v1_0_0/inst/axi_master_ip_v1_0_M00_AXI_inst/m00_axi_wvalid]]
有知道解决方法的，还请不吝赐教。
