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nuts111
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898 次查看
注册日期: ‎09-03-2019

求翻译PG338中的一句话

您好,能不能翻译一下PG338中这句话

Connecting a DPU to the Processing System in the Xilinx SoC

When the AXI slave ports of the PS are insufficient for the DPU, an AXI interconnect for
connection is unavoidable. The two AXI master ports for data fetching are high bandwidth ports
and the AXI master port for instruction fetching is a low bandwidth port. Typically, it is
recommended that all the master ports for instruction fetching connect to the S_AXI_LPD of PS
through one interconnect. The rest of the master ports for data fetching should be directly
connected to the PS as much as possible. Xilinx recommends that the master ports of the DPU
core with higher priority (smaller number, like DPU0) be directly connected to the slave ports of
the PS with higher priority (smaller number, like S_AXI_HP0_FPD).

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zhijiexu
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注册日期: ‎09-29-2020

hi, @nuts111 

这段话的意思就是,在DPU IP的使用中,如果不可避免的要去使用AXI Interconnect的时候,建议将所有的指令传达端口用一个interconnect连接到S_AXI_LPD

将主要的数据端口直接连接到PS上,并建议将序号低的DPU kernel 直接连接到序号低的PS的slave ports, 比如S_AXI_HP0_FPD

希望对您有帮助

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