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Posts: 1
Registered: ‎03-08-2016

AC701 - xapp1097 - Issue with the implemention of a SDI transmitter

Hi everyone

I’m trying to implement a SDI transceiver on an AC701 evaluation board with an Artix7 fpga.

I’ve found the xillinx application note xapp1097 which provides an example of implementation for two SDI RX interfaces and two SDI TX interfaces that are all independent (called “dual SDI demonstration”). I wanted to first run it and then modify it for my own project but I don’t even get this supplied example to work... So that’s why I’m looking for your help :)


The following are the equipment I have:

  • Xilinx Artix-7 FPGA AC701 Evaluation Kit
  • TI SD387EVK evaluation kit (which contains a LMH0387, 3 Gbps HD/SD SDI Configurable I/O Adaptive Cable Equalizer / Cable Driver).
  • Vivado 2015.2

In the application note, instead of the SD387EVK, they use an inrevium TB-FMCH-3GSDI2A SDI FMC board, which in addition to the LMH0387 Cable Equalizer / Cable Driver also provides reference clocks to the GTP Quad (at 148.5 an 148.5/1.001 MHz) and for the DRP clock (at 27MHz).

Since my TI evaluation kit does not provide these clocks, and the 148.5/1.001 MHz one does not seem to be required to generate a HD-SDI signal, I generated the 148 and 27MHz ones with a MMCM and the emcclk (90MHz) available on the AC701 board.

I directly connect the 27MHz clock to the ac701_sdi_demo module and I output the 148.5MHz one to the jitter attenuator on the board (si5324) and connect the output of this last to the GTP Quad 213 through the U3 and U4 clock mux (as illustrated in the figure 1.10 of the ug952).

So I have a top module which instantiate:

  • The ac701_sdi_demo module provided by by the xapp1097
  • A clock wizard IP to generate the 148.5 and 27 MHz clocks
  • A block design which contains a microblaze and an axi iic IP to program the jitter attenuator
  • One OBUFDS to send the 148.5 MHz clock to the jitter attenuator
  • Two IBUFDS_GTE2 to get the resulting two 148.5 MHz clocks for the GTP quad.

So instead of have 148.5 and 148.5/1.1001 MHz at the input of the gtp_common (respectively pll0 and pll1) I put two 148.5 MHz clocks. I verified that I had the correct frequency of 148.5MHz at the output of the clock mux and that my cable driver (TI SD387EVK) was connected to the right pins on my AC701 board (AE7 and AF7 respectively to the tx_p and tx_n of one of the transceiver). The datasheet of the cable driver says that it is configured by default to transmitter HD-SDI mode so I did not program it.

Since I didn’t have anything at the output of my cable driver I had an ILA to the design in order to see if different signals relative to the transmitters had the “correct” value or behavior (tx_refclk_stable, tx_plllock, tx_hd_y, tx_hd_c…).

But when I open the hardware manager and try to trigger the signals I have the following error for the two emitters: “Unable to arm ILA. The core clock is slow or no core clock connected for this ILA or the ILA core may not meet timing. ” but not for the two receivers which are not receiving anything as they are not connected to a SDI source.

Of course I do not expect a direct solution but I would grateful if you can give some advice about how to find what’s wrong with my design…

Are there some signals I can check (lock, enable, ack…) to determine where the problem comes from ?

At which frequency is the generated txoutclk of the GTPE2_CHANNEL ?

I was also wondering if some inputs/attributes of the GTPE2_CHANNEL have to be modified since I do not use the same cable driver as in the application note ?


Thanks in advance