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Explorer
Explorer
338 次查看
注册日期: ‎10-20-2018

关于serdes接口

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最近在看关于serdes的代码时遇到了点问题,没看明白 oq        => dac0_dclk_prebuf是什么含义

硬件程序如下,且附件中也有,谢谢大家了~

----------------------------------------------------------------------------------------------------
--Output serdes and LVDS buffers for clock
----------------------------------------------------------------------------------------------------
  oserdes_inst0 : oserdes
  generic map (
    DATA_RATE_OQ => "DDR",
    DATA_RATE_TQ => "DDR",
    DATA_WIDTH => 4,
    INIT_OQ => '0',
    INIT_TQ => '0',
    SERDES_MODE => "MASTER",
    SRVAL_OQ => '0',
    SRVAL_TQ => '0',
    TRISTATE_WIDTH => 1
  )
  port map (
    oq        => dac0_dclk_prebuf, // 不太懂这句什么意思
    shiftout1 => open,
    shiftout2 => open,
    tq        => open,
    clk       => txclk_64, 
    clkdiv    => txclk_32,
    d1        => '1',
    d2        => '0',
    d3        => '1',
    d4        => '0',
    d5        => '0',
    d6        => '0',
    oce       => '1',
    rev       => '0',
    shiftin1  => '0',
    shiftin2  => '0',
    sr        => oserdes_rst,
    t1        => '0',
    t2        => '0',
    t3        => '0',
    t4        => '0',
    tce       => '0'
  );

----------output buffers
  obufds_lvdsext_25_inst0 : obufds
  port map (
    i  => dac0_dclk_prebuf,
    o  => dac0_dclk_p,
    ob => dac0_dclk_n  //输出时钟信号大小为多少呢?
  );
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Xilinx Employee
Xilinx Employee
270 次查看
注册日期: ‎08-25-2010

回复: 关于serdes接口

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ug471的p163:

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

Thanks
Simon
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Xilinx Employee
Xilinx Employee
294 次查看
注册日期: ‎08-25-2010

回复: 关于serdes接口

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Hi @tranquilsun,

 

OQ应该是数据并->串的输出,D1最先出来。

Thanks
Simon
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Explorer
Explorer
276 次查看
注册日期: ‎10-20-2018

回复: 关于serdes接口

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请问有关于这部分的文档介绍吗?谢谢了

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Xilinx Employee
Xilinx Employee
271 次查看
注册日期: ‎08-25-2010

回复: 关于serdes接口

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ug471的p163:

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

Thanks
Simon
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Don't forget to reply, kudo, and accept as solution.
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