UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

取消
显示结果 
搜索替代 
您的意思是: 
Contributor
Contributor
742 次查看
注册日期: ‎10-16-2018

请教:用k7 FPGA 6个gtx收发器实现6路sdi接口时 placement时报错

请教: vivado 中报错如下 是什么原因导致?

[Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair. The GTXE_COMMON component can use the dedicated path between the GTXE_COMMON and the GTXE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets U_sdi_6ch_top/U_sdi_ch1/gtxe2_common_0/qpllclk] >

U_sdi_6ch_top/U_sdi_ch1/gtxe2_common_0/gtxe2_common_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y0
U_sdi_6ch_top/U_sdi_ch1/SDI1/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y4
U_sdi_6ch_top/U_sdi_ch1/SDI0/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y5

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_gt_bufg
Status: PASS
Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
U_sdi_6ch_top/U_sdi_ch0/SDI0/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X0Y7
U_sdi_6ch_top/U_sdi_ch0/SDI0/SDI/BUFGRX (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

Clock Rule: rule_gtxcommon_gtxchannel
Status: PASS
Rule Description: A GTXCommon driving a GTXChannel must both be in the same clock region
U_sdi_6ch_top/U_sdi_ch0/gtxe2_common_0/gtxe2_common_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y1
U_sdi_6ch_top/U_sdi_ch0/SDI0/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y7
U_sdi_6ch_top/U_sdi_ch0/SDI1/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y6

Clock Rule: rule_bufds_gtxchannel_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXChannel must both be placed in the same or adjacent clock region
(top/bottom)
U_sdi_6ch_top/MGTCLKIN1 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y4
U_sdi_6ch_top/U_sdi_ch1/SDI1/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK1) is locked to GTXE2_CHANNEL_X0Y4
U_sdi_6ch_top/U_sdi_ch1/SDI0/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK1) is locked to GTXE2_CHANNEL_X0Y5
U_sdi_6ch_top/U_sdi_ch0/SDI0/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK1) is locked to GTXE2_CHANNEL_X0Y7
U_sdi_6ch_top/U_sdi_ch0/SDI1/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK1) is locked to GTXE2_CHANNEL_X0Y6

Clock Rule: rule_bufds_gtxcommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region
(top/bottom)
U_sdi_6ch_top/MGTCLKIN0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y2
U_sdi_6ch_top/U_sdi_ch1/gtxe2_common_0/gtxe2_common_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y0
U_sdi_6ch_top/U_sdi_ch0/gtxe2_common_0/gtxe2_common_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y1

Clock Rule: rule_gt_bufg
Status: PASS
Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
U_sdi_6ch_top/U_sdi_ch0/SDI1/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X0Y6
U_sdi_6ch_top/U_sdi_ch0/SDI1/SDI/BUFGRX (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y29

Clock Rule: rule_gt_bufg
Status: PASS
Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
U_sdi_6ch_top/U_sdi_ch1/SDI0/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X0Y5
U_sdi_6ch_top/U_sdi_ch1/SDI0/SDI/BUFGRX (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y25

Clock Rule: rule_gt_bufg
Status: PASS
Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
U_sdi_6ch_top/U_sdi_ch1/SDI1/SDI/GTX_i/gtxe2_i (GTXE2_CHANNEL.RXOUTCLK) is locked to GTXE2_CHANNEL_X0Y4
and U_sdi_6ch_top/U_sdi_ch1/SDI1/SDI/BUFGRX (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y23

 

0 项奖励
6 条回复6
Contributor
Contributor
704 次查看
注册日期: ‎10-16-2018

回复: 请教:用k7 FPGA 6个gtx收发器实现6路sdi接口时 placement时报错

求解^^

0 项奖励
Xilinx Employee
Xilinx Employee
672 次查看
注册日期: ‎08-26-2010

回复: 请教:用k7 FPGA 6个gtx收发器实现6路sdi接口时 placement时报错

Hi @yongkangbi,

 

是否做了参考钟,GTXE2_COMMON_xxxx以及Channel的位置约束?看起来是因为约束不正确导致不能走专用路径导致的错误。

Thanks
Simon
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 项奖励
Community Manager
Community Manager
663 次查看
注册日期: ‎08-31-2011

回复: 请教:用k7 FPGA 6个gtx收发器实现6路sdi接口时 placement时报错

一个quad里有一个common和四个channel。

从报错来看,你ch0是channel的x0y4和x0y5, 对应的应该是common的x0y1,而不是common的x0y0.

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 项奖励
Contributor
Contributor
652 次查看
注册日期: ‎10-16-2018

回复: 请教:用k7 FPGA 6个gtx收发器实现6路sdi接口时 placement时报错

您好,这个约束应该怎么写呢??谢谢!

0 项奖励
Contributor
Contributor
650 次查看
注册日期: ‎10-16-2018

回复: 请教:用k7 FPGA 6个gtx收发器实现6路sdi接口时 placement时报错

您好,没有做位置约束,您能给个这个位置约束的参考么?谢谢
0 项奖励
Xilinx Employee
Xilinx Employee
632 次查看
注册日期: ‎08-26-2010

回复: 请教:用k7 FPGA 6个gtx收发器实现6路sdi接口时 placement时报错

Hi @yongkangbi

可以参考example里的约束来做相应的修改,比如:

set_property LOC AA30 [get_ports  Q0_CLK1_GTREFCLK_PAD_N_IN ]
set_property LOC AA29 [get_ports  Q0_CLK1_GTREFCLK_PAD_P_IN ]

##---------- Set placement for gt0_gth_wrapper_i/GTHE2_CHANNEL ------
set_property LOC GTHE2_CHANNEL_X0Y0 [get_cells xaui_wrapper_support_i/xaui_wrapper_init_i/
inst/xaui_wrapper_i/gt0_xaui_wrapper_i/gthe2_i]
##---------- Set placement for gt1_gth_wrapper_i/GTHE2_CHANNEL ------
set_property LOC GTHE2_CHANNEL_X0Y1 [get_cells xaui_wrapper_support_i/xaui_wrapper_init_i/
inst/xaui_wrapper_i/gt1_xaui_wrapper_i/gthe2_i]
##---------- Set placement for gt2_gth_wrapper_i/GTHE2_CHANNEL ------
set_property LOC GTHE2_CHANNEL_X0Y2 [get_cells xaui_wrapper_support_i/xaui_wrapper_init_i/
inst/xaui_wrapper_i/gt2_xaui_wrapper_i/gthe2_i]
##---------- Set placement for gt3_gth_wrapper_i/GTHE2_CHANNEL ------
set_property LOC GTHE2_CHANNEL_X0Y3 [get_cells xaui_wrapper_support_i/xaui_wrapper_init_i/
inst/xaui_wrapper_i/gt3_xaui_wrapper_i/gthe2_i]

Thanks
Simon
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 项奖励