修改时间 10-19-2019 10:46 PM
i have a question about the axi stream. IN and OUT.
I build an stream input and stream output.
And i control the Mtvalid and Mtlast but i didnt get the data out. In works everything good. But if i make the bitstream i cant see my out. Only when i send +700 data to the Stream port i got an output.
For the test i use the DMA which write to the DDR i put my IPstream between of them(MM2S=>IP=>S2MM) and read the signals with System ILA. My input is good but my output not working.
I look in the documentation and my Signals are correct but i dont know why not working.
Maybe i cant use the DMA for this? i dont know. Someone an idea how to test the stream without DMA?
修改时间 10-20-2019 12:38 AM
Can you share some of the waveforms? Might be helpful to solve your problems.
10-21-2019 09:50 AM - 编辑日期 10-21-2019 09:55 AM
if AXIS master have data m_axis_tvalid will high, then normal you must assert m_axis_tready to get data out; but for example axi ethernet didn't need tready, it just tvalid high ,data out auto.