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Visitor jekot
Visitor
206 次查看
注册日期: ‎08-27-2019

AXI Stream IN OUT

hello,

i have a question about the axi stream. IN and OUT.

I build an stream input and stream output.

And i control the Mtvalid and Mtlast but i didnt get the data out. In works everything good. But if i make the bitstream i cant see my out. Only when i send +700 data to the Stream port i got an output.

For the test i use the DMA which write to the DDR i put my IPstream between of them(MM2S=>IP=>S2MM) and read the signals with System ILA. My input is good but my output not working.

I look in the documentation and my Signals are correct but i dont know why not working.

Maybe i cant use the DMA for this? i dont know. Someone an idea how to test the stream without DMA?

Thank you 

Best regards 

Jekot

 

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3 条回复3
Moderator
Moderator
187 次查看
注册日期: ‎05-23-2018

回复: AXI Stream IN OUT

Hi, @jekot 

Can you share some of the waveforms? Might be helpful to solve your problems.

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Xilinx Employee
Xilinx Employee
104 次查看
注册日期: ‎06-02-2017

回复: AXI Stream IN OUT

Hi @jekot 

It seems that you're using AXIStream Data Fifo IP, right?

What's the configuration of your IP?

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Voyager
Voyager
95 次查看
注册日期: ‎05-29-2018

回复: AXI Stream IN OUT

if AXIS master have data m_axis_tvalid will high,  then normal you must assert m_axis_tready to get data out; but for example axi ethernet didn't need tready, it just tvalid high ,data out auto.

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