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Explorer
Explorer
131 次查看
注册日期: ‎04-06-2017

The configuration related constraint

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By the configuation constaint, I mean CONFIG_VOLTAGE, CFGBVS, CONFIG_MODE etc. I have following questions. 1) Does the configuration constaint have influence during implementation. If I modify these constraint, do I have to rerun implementation? 2) If I set config mode to only JTAG, can I configure FPGA in other mode, for example, slave serial mode by MCU.
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Xilinx Employee
Xilinx Employee
78 次查看
注册日期: ‎08-25-2010

回复: The configuration related constraint

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Hi @greatmaverick 

You can find the information in ug912,

For example, CONFIG_VOLTAGE, the Affected Steps are:
• place_design
• report_drc
• write_bitstream

No JTAG value can be applied to CONFIG_MODE, Since JTAG have a highest priority.

Thanks
Simon
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2 条回复2
Xilinx Employee
Xilinx Employee
79 次查看
注册日期: ‎08-25-2010

回复: The configuration related constraint

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Hi @greatmaverick 

You can find the information in ug912,

For example, CONFIG_VOLTAGE, the Affected Steps are:
• place_design
• report_drc
• write_bitstream

No JTAG value can be applied to CONFIG_MODE, Since JTAG have a highest priority.

Thanks
Simon
-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Explorer
Explorer
70 次查看
注册日期: ‎04-06-2017

回复: The configuration related constraint

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Thank you. I follow your suggestion and read ug912. I have further question. If affected steps is IO planning, do I need to rerun synthesis? What if affected step is report drc? Report drc step exist in both synthesis and implementation.

 

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