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Observer leoeltipo
Observer
248 Views
Registered: ‎12-11-2017

Artix-7 SelectIO wizard erratic

Hello,

I am working on a controller for receiving data from a ADC. The ADC works at 15 MSPS and data is 18-bit. I am using a 150 MHz clock with DDR at the FPGA side. For implementing the deserializer, I am using the SelectIO wizard. It should be straightforward, however, I have been fighting with it for a month or so and cannot get the controller working.

The ADC forwards the clock aligned with the two data lanes. If I check with a scope, data and clock are properly aligned (custom board, careful PCB design). If I understand the SelectIO, I should add a small delay on the data and use bitslip for correct framing. I cannot get the right delay to find the right pattern (the ADC provides a training pattern).

Which is worse, is that I do not get consistent results. If I change the delay or even if I do small changes on the firmware, data is not the same over successive implementations. The usage of the SelectIO wizard should give consistent results, as all the pins were carefully selected to share the buffers/idelay/iserdes right next to them.

If anyone can provide a way to properly selecting the delay, please let me know that would be of a big help.

Regards,

Leoeltipo

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12 Replies
Scholar dpaul24
Scholar
237 Views
Registered: ‎08-07-2014

Re: Artix-7 SelectIO wizard erratic

@leoeltipo,

The usage of the SelectIO wizard should give consistent results, as all the pins were carefully selected to share the buffers/idelay/iserdes right next to them.

If anyone can provide a way to properly selecting the delay, please let me know that would be of a big help.

Have you tried playing around with the set_input_delay in the constrain file instead of the delay in SelectIO wizard ?

 

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FPGA enthusiast!
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Observer leoeltipo
Observer
203 Views
Registered: ‎12-11-2017

Re: Artix-7 SelectIO wizard erratic

It is supposed that I use the wizard because it should use the iserdes right next to the pins. Pins were carefully selected before building the board. The wizard is impossible. Cannot make it work by any means. Trying to instantiate the internal iserdes and idelay by hand, and simulation does not even work. Did xilinx test this IP?

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Moderator
Moderator
197 Views
Registered: ‎04-18-2011

Re: Artix-7 SelectIO wizard erratic

Hi @leoeltipo

The wizard builds what you tell it to out of the idelays and the iserdes with the specified clocking

There is no real intelligence built in to it at all. 

If you look at some of the xapp documents like xapp585 and xapp524 you will see that there is usually some sort of logic that moves the clock to the centre of the data eye or reposition it in the middle of the eye as the case may be...once this is done you will have the bitslip done to check the alignment

Tell us how you clock this interface, is it ddr or SDR? Have you ensured that the interface is taken out of reset synchronous to CLKDIV? How do you manage 18bits of data?

 

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Observer leoeltipo
Observer
180 Views
Registered: ‎12-11-2017

Re: Artix-7 SelectIO wizard erratic

Hi,

My interfase is DDR. I read 18 bits by using 2 lanes in 1:10 (DDR) which gives me 20 bits. All lines coming back from the ADC are properly length and impedance matched, so data is perfectly aligned in the pins of the FPGA.

Regarding the reset, I instantiated a system reset block to let the clock reset to go first and then the io reset. Reset is synchronous to the divided clock. Is it possible to be related to the reset? There are no state machines inside the selectio.

We took the pins very carefully before designing the board. It was supposed the selectio should be simple...

Regards,

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Moderator
Moderator
150 Views
Registered: ‎04-18-2011

Re: Artix-7 SelectIO wizard erratic

Ok so a couple of points:

I always check that the deassertion of the reset is synchronous to CLKDIV. not doing this can cause you to end up with alignment issues.

How is the Iserdes clocked? There are only 2 valid ways

Frame clock comes in and you multiply it up using the mmcm then you clock both the serial clock and CLKDIV with a bufg

Or you receive the bit clock and this drives a bufio/bufr pair to clock CLK and CLKDIV

Once we understand the clocking topology we can try to understand why you are not getting sensible data. 

Even if properly aligned at the input you can still get some skew at the iserdes if clock and data take 2 different paths inside the fpga. You should read xapp524 about allinging the clock and data. 

Are you using an ILa look at what's going on. 

You mentioned you cannot find the training pattern that is sent

Check what is really going on here. Is it lost and constantly bit slipping.

 

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Observer leoeltipo
Observer
130 Views
Registered: ‎12-11-2017

Re: Artix-7 SelectIO wizard erratic

Hello,

I receive bit clock on the pins together with data (two lanes, everything differential). The wizard is doing what you say. BUFIO for the clock and BUFR with the division for CLKDIV. Pins are next to each other. If I look at the device view after implementation, everything is where it should to ensure low delay. Indeed, according to the appnote you mention, specific point-to-point connections between idelay/iserdes should be available and used when chosing the right pins. 

Everything looks properly connected, but data is not good. We found a work-around using a internal clock and not using at all the forwarded clock from the AD. It does not have any sense as we picked the pins not to do this...

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Historian
Historian
122 Views
Registered: ‎01-23-2009

Re: Artix-7 SelectIO wizard erratic

You seem to be under a mistaken impression as to what the SelectIO wizard does for you. The SelectIO wizard is really just (supposed to be) a quicker way of instantiating the ISERDES, IDELAY and clock buffer cells rather than hand instantiating them.

As others have said, this wizard has no intelligence at all - it in no way guarantees that the interface is captured properly or even that it is capturable. With any high interface, it is the designer's job to architect a working capture mechanism - these become more complicated as the data rates increase.

The first thing to determine is if the interface is going to be captured statically or dynamically. If the width of each bit on the interface is wide enough after all external device and board uncertainties, then you can capture it statically - depending on the device family and speedgrade, this is generally possible with input windows that are larger than 1.5-2.0ns (above around 2.0ns these get relatively easy). If you are below this threshold then you need to use some kind of dynamic calibration similar to XAPP524. But, beware, dynamic interfaces are tricky and are hard to validate - static capture should always be used if it is possible. This, of course, all assumes that your clock and data inputs meet the requirements of the clocking architecture you end up with (clocks on clock capable pins, and, for some architectures, all related data in the same bank as the clock).

If you are using static capture, you can use a variety of clock architectures and clock/data phase alignment mechanisms. You, the designer, must choose and analyze the proper mechanism and then communicate that to the tool with the proper architecture (whether hand instantiated or by the SelectIO Wizard) and constraints. Once you have done this, the tools will tell you if the interface will work or not - if the architecture you specified will capture an interface with the constraints you specified. Take a look at this post on input capture clock architectures and this post on constraining DDR interfaces.

Finally, even once you have the proper capture mechanism, you then need to worry about framing. Again, the SelectIO wizard does not perform framing for you - you have to design the mechanism to do so. The "bitslip" mechanism of the ISERDES gives you a mechanism to change the framing alignment, but you need to design the statemachine and pass/fail detector to drive the bitslip to get to the proper alignment.

Avrum

Observer leoeltipo
Observer
114 Views
Registered: ‎12-11-2017

Re: Artix-7 SelectIO wizard erratic

Hello again,

I understand the IP does not have any intelligence and that the tool does not solve what I should. I also understand that it is just a delay and a shift register, but on the right spot to avoid timing problems.

My data clock is 150 MHz DDR, which means a bit width of 3.33 ns. That should be slow enough not to pose any troubles. As I said, using a internally generated clock it works, but I have to place with the phase a little bit due to the delay of the clock respect to the data. Using the forwarded clock from the AD should be easier. This clock is not created by a PLL at the AD converter itself, it is just a forwarded version of the clock that is created and sent by the FPGA to the device, so it should be ok.

I understand bitslip is for framing, but what it does is only shifting (left or right) the first bit of the work with respect to the divided clock signal. So I should be able to find my bits even without bitslip.

Again, I know the tool does not do any magic, but when designing a custom board with chose the pins being confident that the specs will be respected and the IP will work.

Thank you for your ideas.

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Historian
Historian
106 Views
Registered: ‎01-23-2009

Re: Artix-7 SelectIO wizard erratic

...but on the right spot to avoid timing problems

No. This is not the case. It is your responsibility to ensure that the interface meets timing.

I understand bitslip is for framing, but what it does is only shifting (left or right) the first bit of the work with respect to the divided clock signal.

There is nothing magic about bitslip - it is just an easier (and less expensive in terms of FPGA resources) barrel shifter on the data.

Another common misconception in ADC interfaces is that the "Frame Clock" provided by some ADCs is to be used as a clock in the FPGA. Generally it is not - it is treated as data. If your ADC provides a bit clock (often called DCO) and a frame clock (often called FCO) then you only use the DCO for clocking. While the FCO is the right frequency for the "CLKDIV" of an ISERDES, the phase is not acceptable - you must use a divided version of DCO that was generated inside the FPGA - either with the BUFR (if you are using BUFIO/BUFR clocking) or with the MMCM (if you are using MMCM clocking). The FCO is sampled like the data bits, and is used to determine framing; when your interface is properly framed the sampled value from the FCO ISERDES will be 11110000 (assuming 8x oversampling); the 0-1 transition of FCO is captured in the first bit of your framed capture. Often this FCO is the only thing required for your framing state machine - if you don't have the right pattern, assert bitslip (on your FCO and data capture ISERDESes) until you get the right pattern.

Avrum

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Observer leoeltipo
Observer
102 Views
Registered: ‎12-11-2017

Re: Artix-7 SelectIO wizard erratic

Hello,

I do receive a bit clock (DCO) and I am using only this for bit reading. The divided clock is derived from there with a bufr. I do not have any framing clock.

Regarding the constraints and timing, I do not have much to do here. Only ensure timing is met. But I cannot constrain neither the DCO or Data lines as they are connected to the site Differential input, and that goes straight to the idelay/iserdes right next to it. Those lines are not routed with share routing resources, they are one-to-one connection and there is nothing to do there. This connections are like so to ensure delays are matched.

Again, I understand the block could not be plug and play, but with the right selection of the pins plus the proper length+impedance matching of the PCB (which is already verified), this should not take that much of effort.

Attached you will find a detail of the resources of the FPGA. As you can see, the two lanes of input data were properly chosen to be right next to each other. The output of the differential input buffer is routed to the idelay using a dedicated routing point to point connection according to xilinx. I cannot do any better to improve matching here. The other picture is the forwarded clock from the ADC (DCO as you said). Again, the clock pin is right next to the BUFIO+BUFR combination, as we read the datasheet before chosing those pins in our board.

Even if you insist there must be some extra control here to be able to read the bits, I would think that if the IP does not work in this scenario, it had not been tested, as we followed all the recommendations from a package and PCB point of view.

Regards,

Leandro

Diff-data.jpg
Diff-clock.jpg
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Historian
Historian
96 Views
Registered: ‎01-23-2009

Re: Artix-7 SelectIO wizard erratic

I do receive a bit clock (DCO) and I am using only this for bit reading. The divided clock is derived from there with a bufr. I do not have any framing clock.

Good - this sounds correct. However, if you have no framing clock, how do you determine framing? From the fixed pattern generation?

Even if you insist there must be some extra control here to be able to read the bits, I would think that if the IP does not work in this scenario, it had not been tested, as we followed all the recommendations from a package and PCB point of view.

I'm sorry - but this is just not correct.

There is absolutely nothing that says that the setup/hold requirement of an IOB flip-flop is centered around the rising edge of the clock - in fact it isn't. Since you are using ChipSync clocking (the BUFIO and BUFR) - if you look at the datasheet for the Artix-7 (DS181) in the secton Device Pin-to-Pin Input Parameter Guidelines, it gives you a value for Tpscs/Tphcs - this clearly shows that the setup/hold window for this configuration is not centered around the rising edge of the clock - the required window is entirely after the clock edge. And these numbers are guidelines only - the real numbers must be obtained from the tool.

And this is exactly why you need constraints. While you are right that the connections in this system are fixed and are not affected by routing - the only way to have the tool tell you if you are meeting the setup/hold requirements of the FPGA is to provide the tool with proper input constraints and have it analyze the margins on this interface.

Avrum

Observer leoeltipo
Observer
50 Views
Registered: ‎12-11-2017

Re: Artix-7 SelectIO wizard erratic

Ok,

Can I then ask you how to constrain those inputs?

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