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Visitor caoimhe
Visitor
728 Views
Registered: ‎11-09-2017

Block Design Ports

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Hi all,

 

I'm placing my IP in a block diagram for the Arty board and have 3 64-bit IOs in the design. The Synthesis tool assigned each bit a port. Do I need to create 192 ports on the diagram and hook each of the bits to its assigned port in order to get the design working correctly on the board, or is there a better way to approach it?

 

Thanks in advance! 

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Moderator
Moderator
1,051 Views
Registered: ‎04-18-2011

Re: Block Design Ports

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Hi @caoimhe

 

I am not sure I follow you.

 

If I do something simple like this to mimic your IP. 

 

module top_caoimhe(
input clk,
input reset,
input [63:0] data_in,
output reg [63:0] data_out
);

always@(posedge clk)begin
if(reset)
data_out <= 64'd0;
else
data_out <= data_in;
end
endmodule

 

and drop it into my block design it should keep the buses 

 

caoimhe_bd.PNG

 

I just click on the outputs in an do make external.

 

if they are not part of a bus then you could script it in vivado. 

first make a variable in tcl to hold all the IP pins.

set my_ip_pins [get_bd_pins top_caoimhe_0/*]

then do make external

make_bd_pins_external $my_ip_pins

 

After you synthesize the design you will have to lock the inputs and outputs to a physical pin on the package via the XDC file. 

 

 

 

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6 Replies
Moderator
Moderator
1,052 Views
Registered: ‎04-18-2011

Re: Block Design Ports

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Hi @caoimhe

 

I am not sure I follow you.

 

If I do something simple like this to mimic your IP. 

 

module top_caoimhe(
input clk,
input reset,
input [63:0] data_in,
output reg [63:0] data_out
);

always@(posedge clk)begin
if(reset)
data_out <= 64'd0;
else
data_out <= data_in;
end
endmodule

 

and drop it into my block design it should keep the buses 

 

caoimhe_bd.PNG

 

I just click on the outputs in an do make external.

 

if they are not part of a bus then you could script it in vivado. 

first make a variable in tcl to hold all the IP pins.

set my_ip_pins [get_bd_pins top_caoimhe_0/*]

then do make external

make_bd_pins_external $my_ip_pins

 

After you synthesize the design you will have to lock the inputs and outputs to a physical pin on the package via the XDC file. 

 

 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Visitor caoimhe
Visitor
666 Views
Registered: ‎11-09-2017

Re: Block Design Ports

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Thanks @klumsde. I was worried it wouldn't connect them without the physical pins on the block diagram itself, but it will be automatically done once they're assigned in the XDC? 

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Moderator
Moderator
662 Views
Registered: ‎04-18-2011

Re: Block Design Ports

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Hi Caoimhe,
No. By making the pins on your IP external you just makes them top level ports in the design.
After that the top level ports need to be assigned a physical pin on the device/package in the XDC and also they need an IO standard.

set_property PACKAGE_PIN AN3 [get_ports driver_out]
set_property IOSTANDARD LVCMOS18 [get_ports driver_out]
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Visitor caoimhe
Visitor
658 Views
Registered: ‎11-09-2017

Re: Block Design Ports

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That's great, thanks a mil!

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Observer luckfyzhang
Observer
96 Views
Registered: ‎10-14-2017

Re: Block Design Ports

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Hi,

 There seems no make_bd_pins_external command on my tcl console. I am wondering are you referring to other similar command? 

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Moderator
Moderator
93 Views
Registered: ‎04-18-2011

Re: Block Design Ports

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The syntax below works for me. 

make_bd_pins_external [get_bd_pinsmy_ip/some_signal]

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