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Visitor demonpopo
Visitor
2,397 Views
Registered: ‎02-04-2016

Can't debug my project in SDK 2016.4

Dear Sir,

 

I use XC7Z035FBG676-1 FPGA.

 

I can download bitstram  through Vivado.

 

I use Zynq in my design, I can't debug usu SDK

It have below error:

 

xsct% mrd 0x00100000
xsct% Context does not support memory read. Unsupported command

Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xffffff28 (Suspended)
Info: ARM Cortex-A9 MPCore #1 (target 3) Stopped at 0xffffff34 (Suspended)
Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0x0 (Vector Catch)
Downloading Program -- D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_sw/Debug/new_sw.elf
    section, .text: 0x00100000 - 0x001016eb
    section, .init: 0x001016ec - 0x00101703
    section, .fini: 0x00101704 - 0x0010171b
    section, .rodata: 0x0010171c - 0x00101733
    section, .data: 0x00101738 - 0x00101bab
    section, .eh_frame: 0x00101bac - 0x00101baf
    section, .mmu_tbl: 0x00104000 - 0x00107fff
    section, .init_array: 0x00108000 - 0x00108003
    section, .fini_array: 0x00108004 - 0x00108007
    section, .bss: 0x00108008 - 0x0010802f
    section, .heap: 0x00108030 - 0x0010a02f
    section, .stack: 0x0010a030 - 0x0010d82f
aborting, 1 pending requests...
Failed to download D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_sw/Debug/new_sw.elf
Info: ARM Cortex-A9 MPCore #0 (target 2) Running (APB AP transaction error, DAP status f0000021)
xsdb% Info: ARM Cortex-A9 MPCore #1 (target 3) Running (APB AP transaction error, DAP status f0000021)
xsdb%


//3

20:07:36 INFO    : Launching XSCT server: xsct.bat -interactive D:\code_test\Vivado_2016.4_FMCOMMS3\SPI_test\Green_xc7z035_spi_test\SDK\temp_xsdb_launch_script.tcl
20:07:36 INFO    : XSCT server has started successfully.
20:07:36 INFO    : Successfully done setting XSCT server connection channel  
20:07:36 INFO    : Successfully done setting SDK workspace  
20:07:36 INFO    : Registering command handlers for SDK TCF services
20:07:41 INFO    : SDK has detected change in the last modified timestamps for source hardware specification file Source:1501243553910,  Project:1501242973662
20:07:41 INFO    : Project new_hw's source hardware specification located at D:\code_test\Vivado_2016.4_FMCOMMS3\SPI_test\Green_xc7z035_spi_test\Green_xc7z035_spi_test.sdk\test_top.hdf is now different from the local copy.
         The local copy will be replaced with the source specification and your workspace will be updated.
20:07:42 INFO    : Copied contents of D:\code_test\Vivado_2016.4_FMCOMMS3\SPI_test\Green_xc7z035_spi_test\Green_xc7z035_spi_test.sdk\test_top.hdf into \new_hw\system.hdf.
20:07:45 INFO    : Synchronizing projects in the workspace with the hardware platform specification changes.
20:07:46 INFO    :
20:07:48 INFO    : Updating hardware inferred compiler options for new_sw.
20:07:48 INFO    : Clearing existing target manager status.
20:07:50 INFO    : Closing and re-opening the MSS file of ther project new_sw_bsp
20:07:51 INFO    : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
20:07:52 WARN    : Linker script will not be updated automatically. Users need to update it manually.
20:08:14 INFO    : Connected to target on host '127.0.0.1' and port '3121'.
20:08:29 INFO    : Connected to target on host '127.0.0.1' and port '3121'.
20:08:29 INFO    : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB 00000000000000" && level==0} -index 1' command is executed.
20:08:59 INFO    : FPGA configured successfully with bitstream "D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/test_top.bit"
20:09:04 INFO    : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB 00000000000000" && level==0} -index 1' command is executed.
20:09:04 INFO    : 'fpga -state' command is executed.
20:09:04 INFO    : Connected to target on host '127.0.0.1' and port '3121'.
20:09:04 INFO    : Jtag cable 'Platform Cable USB 00000000000000' is selected.
20:09:04 INFO    : 'jtag frequency' command is executed.
20:09:04 INFO    : Sourcing of 'D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/ps7_init.tcl' is done.
20:09:04 INFO    : Context for 'APU' is selected.
20:09:04 INFO    : Hardware design information is loaded from 'D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/system.hdf'.
20:09:04 INFO    : Context for 'APU' is selected.
20:09:05 INFO    : 'stop' command is executed.
20:09:06 INFO    : 'ps7_init' command is executed.
20:09:06 INFO    : 'ps7_post_config' command is executed.
20:09:06 INFO    : Context for processor 'ps7_cortexa9_0' is selected.
20:09:06 INFO    : Processor reset is completed for 'ps7_cortexa9_0'.
20:09:06 INFO    : Context for processor 'ps7_cortexa9_0' is selected.
20:09:08 ERROR    : Memory write error at 0x100000. APB AP transaction error, DAP status f0000021
20:09:08 INFO    : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/ps7_init.tcl
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
loadhw D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/system.hdf
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
dow D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_sw/Debug/new_sw.elf
----------------End of Script----------------

20:10:51 INFO    : Connected to target on host '127.0.0.1' and port '3121'.
20:10:51 INFO    : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB 00000000000000" && level==0} -index 1' command is executed.
20:11:20 INFO    : FPGA configured successfully with bitstream "D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/test_top.bit"
20:11:24 INFO    : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB 00000000000000" && level==0} -index 1' command is executed.
20:11:24 INFO    : 'fpga -state' command is executed.
20:11:24 INFO    : Connected to target on host '127.0.0.1' and port '3121'.
20:11:25 INFO    : Jtag cable 'Platform Cable USB 00000000000000' is selected.
20:11:25 INFO    : 'jtag frequency' command is executed.
20:11:25 INFO    : Sourcing of 'D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/ps7_init.tcl' is done.
20:11:25 INFO    : Context for 'APU' is selected.
20:11:25 INFO    : Hardware design information is loaded from 'D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/system.hdf'.
20:11:25 INFO    : Context for 'APU' is selected.
20:11:25 INFO    : 'stop' command is executed.
20:11:26 INFO    : 'ps7_init' command is executed.
20:11:26 INFO    : 'ps7_post_config' command is executed.
20:11:26 INFO    : Context for processor 'ps7_cortexa9_0' is selected.
20:11:26 INFO    : Processor reset is completed for 'ps7_cortexa9_0'.
20:11:26 INFO    : Context for processor 'ps7_cortexa9_0' is selected.
20:11:29 ERROR    : Memory write error at 0x100000. APB AP transaction error, DAP status f0000021
20:11:29 INFO    : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/ps7_init.tcl
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
loadhw D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/system.hdf
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
dow D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_sw/Debug/new_sw.elf
----------------End of Script----------------

20:21:15 INFO    : Connected to target on host '127.0.0.1' and port '3121'.
20:21:15 INFO    : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB 00000000000000" && level==0} -index 1' command is executed.
20:21:44 INFO    : FPGA configured successfully with bitstream "D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/test_top.bit"
20:22:14 INFO    : SDK has detected change in the last modified timestamps for source hardware specification file Source:1501244498925,  Project:1501243553910
20:22:14 INFO    : Project new_hw's source hardware specification located at D:\code_test\Vivado_2016.4_FMCOMMS3\SPI_test\Green_xc7z035_spi_test\Green_xc7z035_spi_test.sdk\test_top.hdf is now different from the local copy.
         The local copy will be replaced with the source specification and your workspace will be updated.
20:22:17 INFO    : Copied contents of D:\code_test\Vivado_2016.4_FMCOMMS3\SPI_test\Green_xc7z035_spi_test\Green_xc7z035_spi_test.sdk\test_top.hdf into \new_hw\system.hdf.
20:22:20 INFO    : Synchronizing projects in the workspace with the hardware platform specification changes.
20:22:22 INFO    :
20:22:23 INFO    : Updating hardware inferred compiler options for new_sw.
20:22:23 INFO    : Clearing existing target manager status.
20:22:23 INFO    : Closing and re-opening the MSS file of ther project new_sw_bsp
20:22:23 INFO    : Workspace synchronized with the new hardware specification file. Cleaning dependent projects...
20:22:24 WARN    : Linker script will not be updated automatically. Users need to update it manually.
20:23:22 ERROR    : (XSDB Server)Context does not support memory read. Unsupported command

20:23:40 INFO    : 'targets -set -filter {jtag_cable_name =~ "Platform Cable USB 00000000000000" && level==0} -index 1' command is executed.
20:23:40 INFO    : 'fpga -state' command is executed.
20:23:40 INFO    : Connected to target on host '127.0.0.1' and port '3121'.
20:23:40 INFO    : Jtag cable 'Platform Cable USB 00000000000000' is selected.
20:23:40 INFO    : 'jtag frequency' command is executed.
20:23:40 INFO    : Sourcing of 'D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/ps7_init.tcl' is done.
20:23:40 INFO    : Context for 'APU' is selected.
20:23:40 INFO    : Hardware design information is loaded from 'D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/system.hdf'.
20:23:40 INFO    : Context for 'APU' is selected.
20:23:40 INFO    : 'stop' command is executed.
20:23:41 INFO    : 'ps7_init' command is executed.
20:23:41 INFO    : 'ps7_post_config' command is executed.
20:23:41 INFO    : Context for processor 'ps7_cortexa9_0' is selected.
20:23:41 INFO    : Processor reset is completed for 'ps7_cortexa9_0'.
20:23:41 INFO    : Context for processor 'ps7_cortexa9_0' is selected.
20:23:44 ERROR    : Memory write error at 0x100000. APB AP transaction error, DAP status f0000021
20:23:44 INFO    : ----------------XSDB Script----------------
connect -url tcp:127.0.0.1:3121
source D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/ps7_init.tcl
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
loadhw D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_hw/system.hdf
targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
stop
ps7_init
ps7_post_config
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
rst -processor
targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Platform Cable USB 00000000000000"} -index 0
dow D:/code_test/Vivado_2016.4_FMCOMMS3/SPI_test/Green_xc7z035_spi_test/SDK/new_sw/Debug/new_sw.elf
----------------End of Script----------------

Why have this issue?

0 Kudos
3 Replies
Explorer
Explorer
2,374 Views
Registered: ‎04-05-2016

Re: Can't debug my project in SDK 2016.4

Can you connect to the part using Hardware Manager in Vivado and get the temperature out of it successfully?It looks like it may be in reset or the JTAG chain is not setup correctly.

 

Also, are you running the ps7_init when you start debugging?  You'll want to "Reset entire system", "Program FPGA", "Run ps7_init", and "Rung ps7_post_config" when debugging.

 

 

ps3_init_sdk.PNG
Visitor demonpopo
Visitor
2,365 Views
Registered: ‎02-04-2016

Re: Can't debug my project in SDK 2016.4

Hi Sir,

I can using Hardware Manager in Vivado download Bitstream.

In SDK I have set this "Reset entire system", "Program FPGA", "Run ps7_init", and "Rung ps7_post_config"

But It can't work success.

擷取.JPG

 

擷取.JPG

 

 

擷取.JPG

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Newbie john@stone
Newbie
92 Views
Registered: ‎11-28-2018

Re: Can't debug my project in SDK 2016.4

Thank you! That solved my problem
0 Kudos