01-04-2019 11:14 AM
I try route clock throught BUFG.
PAD -> IBUFDS -> BUFG -> OBUFDS -> PAD.
In implementation I see that delay from IBUFDS to BUFG is about 2600 ps.How can I change delay to, for example, 3500 ps?
P.S. Please tell me the method without using IDELAY. Thanks.
01-07-2019 12:40 AM
Can you explain why you wish to do this?
If your input is a clock capable IO and you go to a BUFG, you don't have much scope to really change the net delay.
I guess the only way to modify the net delay would be to experiment with different BUFGs but I doubt you will have the scope to really change the delay to your liking.
In this case maybe the thing to do is use the MMCM to deskew the clock and apply a phase shift to it.
So the connectivity should be something like:
PAD -> IBUFDS -> MMCM (Apply a phase shift to the output) -> BUFG -> ODDR -> OBUFDS -> PAD
01-07-2019 01:18 AM
If the IO is a clock capable pin then the path to the BUFGs is largely fixed I expect.
You won't be able to tell the tools to pick a route of a given length.
why not try the phase shift with the MMCM?