UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
427 Views
Registered: ‎06-22-2018

Decoupling VREFCA or VREFDQ to VDD in DDR3 design

In ZedBoard's DDR3 design, the VREFCA and VREDDQ not only decoupled to GND, but also to VDD/VDDQ. But in other boards, such as MicroZed or ZC702, the pin only decoupled to GND.

 

Note: The schematic shows VREFCA decoupled to VDD, and VREFDQ decoupled to GND.

 

Are there any advantages to decouple it both to GND and VDD?

 

1.png

Tags (2)
0 Kudos
1 Reply
407 Views
Registered: ‎01-08-2012

Re: Decoupling VREFCA or VREFDQ to VDD in DDR3 design

Two hypothetical advantages:

 

1.  (If we assume that the power supply impedance is zero) using two caps will halve the high frequency impedance seen by the Vref pin (when compared to a single capacitor), assuming the two capacitors are located appropriately.

 

2.  Vref is supposed to track the supply voltage divided by 2.  Using two capacitors of equal capacitance makes a voltage divider that will correctly track the short term variations in the supply voltage (as opposed to a single cap to ground that will act as a low pass filter and NOT track the short term variations in the supply voltage).

 

 

BTW, If there was no noise and a perfect PCB layout, neither point would matter.  But there is always noise, and PCB layouts are always a compromise between several conflicting requirements.

0 Kudos