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Observer elphel
Observer
7,161 Views
Registered: ‎08-09-2013

Driving BUFIO from the general interconnect

Is it possible to drive BUFIO from the fabric? UG472 says that:

"BUFIOs are driven by:
• SRCCs and MRCCs in the same clock region
• MRCCs in an adjacent clock region using BUFMRs
• MMCMs clock outputs 0-3 driving the HPC in the same clock region
• General interconnect"

But I can not make it work. I'm trying to drive a clock buffer from IDELAYE2 and use the clock (CLK input) for ISERDESE2. Tools allow me to use BUFR (after using "set_property CLOCK_DEDICATED_ROUTE FALSE ..." for the IDELAYE2 output signal), but the same does not work with BUFIO.

 

Is it a typo in UG472 (and BUFIO does not allow "General interconnect") or I'm doing something else wrong?

 

Andrey Filippov

Elphel, Inc.

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4 Replies
Community Manager
Community Manager
7,134 Views
Registered: ‎06-14-2012

Re: Driving BUFIO from the general interconnect

The BUFIO and BUFR buffers are used for regional clocks that do not need to reach all regions of the device. They are typically used for clocking IOSERDES interfaces.When driving the ISERDES/OSERDES CLK and CLKDIV pins, use BUFIOs in conjunction with BUFRs that have their divide capability activated. The BUFIO drives a clean, low-skew clock to the CLK port of the ISERDES/OSERDES and the BUFR drives the slower CLKDIV input.These networks can drive only the clock ports of the ILOGIC/OLOGIC resources and the high-speed clock ports (CLK) of the ISERDES/OSERDES Each I/O clock network is driven by a BUFIO

 

For your clocking , Please refer the ISERDES2 clocking interface in SelectIO Users Guide.

The only valid configuration are below. This could be the reason on why it’s not working.

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

 

Capture.PNG
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Moderator
Moderator
7,131 Views
Registered: ‎02-16-2010

Re: Driving BUFIO from the general interconnect

Check with SelectIO wizard to setup the ISERDES, IDLEAY2 (on clock and data). It will provide an example design for your requirement. The snapshot below shows setting up IDELAY on clock and data path through selectio wizard.selectio.JPG

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Observer elphel
Observer
7,119 Views
Registered: ‎08-09-2013

Re: Driving BUFIO from the general interconnect

Hello Venkata, thank you for your recommendations.

I do not use Vivado GUI and wizards, just pure Verilog + constraints file. I had poor experiecwe with MIG wizard last year as it did not allow me to attach a single-chip x16 DDR3 to XC7Z030-1FBG484C to HP34 (I used internal VREF and DCI cascade, no CS) when I was designing a new board. Additionally MIG uses some undocumented features of the chip that can not be simulated with my software of choice (I use Icarus+GTKWave), so I'm working on a DDR3 controller from scratch. It seems that 4 of the BUFR are sufficient for my design, but I still would like to understand - what is wrong with my use of BUFIO.

Here are the snippets:

//set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets dqs_single_i/dqs_in_dly_i/dqs_read]
//BUFR                          iclk_i    (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint above
BUFIO                          iclk_i    (.O(iclk),.I(dqs_read)); // Fails even with the constraint

.xdc file:

#    inout       dqs,
set_property PACKAGE_PIN N7 [get_ports {dqs}]
set_property SLEW FAST [get_ports {dqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {dqs}]

#    inout       ndqs,
set_property PACKAGE_PIN N6 [get_ports {ndqs}]
set_property SLEW FAST [get_ports {ndqs}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {ndqs}]


#    inout        dq,
set_property IOSTANDARD SSTL15_T_DCI [get_ports {dq}]
set_property PACKAGE_PIN F6 [get_ports {dq}]

...

the source of the dqs_read is IDELAYE2.DATAOUT, driven by IOBUFDS_DCIEN . iclk in this test goes to a single ISERDESE2.CLK input (and .CLKB(~iclk) ), this element is in the same HP34 bank.

When I use BUFR (commented out line above) - everything is placed and routed, but with BUFIO (no other changes, just comment one line, uncomment another), I get:

Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1127.488 ; gain = 494.773
INFO: [Netlist 29-17] Analyzing 18 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
Parsing XDC File [/home/elphel/vdt/eddr3/phy/test_dqs07_placement.xdc]
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance dqs_single_i/iobufs_dqs_i/IBUFDS/IBUFDS_M at N7 (IOB_X1Y120) since it belongs to a shape containing instance iclk_i. The shape requires relative placement between dqs_single_i/iobufs_dqs_i/IBUFDS/IBUFDS_M and iclk_i that cannnot be honored because it would result in an invalid location for iclk_i. [/home/elphel/vdt/eddr3/phy/test_dqs07_placement.xdc:2]

Both source and destination for BUFIO are in the same HP34 bank, and as I mentioned above BUFR works just fine.

 

What I also do not understand - why reported error is about placing a port, not about the clock buffer? Ports are on the PCB and can not be changed, clock buffers are internal resources. So it seems more logical to me if the ports were placed unconditionally where constraints specify (reporting just IOSTANDARD incompatible/nonexistent pins) and DRC reporting the problems of the instantiating/connecting internal resources. Or is there other rationale for this behavior?

 

Andrey Filippov

Elphel, Inc.

 

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Observer elphel
Observer
7,107 Views
Registered: ‎08-09-2013

Re: Driving BUFIO from the general interconnect

Here is that test file I was trying to process, as well as the other related source files

https://github.com/Elphel/eddr3/blob/master/phy/test_dqs07.v

 

Andrey Filippov

Elphel, Inc.

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