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Observer carven
Observer
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Registered: ‎02-09-2011

How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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Hi,

 

I remember I have read some people use a trick to divide the clock by 2 with a simple primitive (Nexys4 / Nexys4 DDR, that is Artix-7 chip). But I can't find the git now.

 

It seems there are certain primitive that is dedicated to divide clock by 2 without configuring the parameter.

 

Did anyone help me that how to do it?

 

I am designing a tutorial, and I want to simplifying the instruction and make students focused on the other point, so I don't want to   invoking the Clock Wizard in the lab. The origin clock is 100MHz and I use ISE for the fpga development.

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Moderator
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Registered: ‎11-09-2015

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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Hi @carven,

 

You can use a BUFGCE and toggle the CE input every 2 clock cycles. See UG768 p77 for the BUFGCE primitive.

 

Hope that helps,

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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Hi @carven,

 

You can use a BUFGCE and toggle the CE input every 2 clock cycles. See UG768 p77 for the BUFGCE primitive.

 

Hope that helps,

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Voyager
Voyager
8,257 Views
Registered: ‎06-24-2013

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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@carven

 

The 7 Series BUFR (Regional Clock Buffer) primitive has a BUFR_DIVIDE attribute which can be configured from 1 to 8.

 

Note that not all divisions will result in 50% duty cycle, specifically all divisions by an odd number will be off.

 

Hope that helps,

Herbert

-------------- Yes, I do this for fun!
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Historian
Historian
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Registered: ‎01-23-2009

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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The 7 Series BUFR (Regional Clock Buffer) primitive has a BUFR_DIVIDE attribute which can be configured from 1 to 8.

 

Be aware that the BUFR is a regional clock buffer, and, as such, is intended for use in specific clocking structures. You should not treat this as a general purpose clock divider - it is specifically intended for dividing an incoming clock (or in certain cases a high performance clock) to generate the CLKDIV for an ISERDES/OSERDES.

 

For more general purpose clock division, you should probably consider using an MMCM or PLL, or the BUFGCE solution. Note that even with all of those, the structure around the actual clock division needs to be designed correctly if you want to be able to know the phase of the divided clock (i.e. have it in phase with other clocks related to it). For example, to use the BUFGCE and have the divided clock be in phase with the non-divided clock, it must be in parallel with a (non-gated) BUFG, as shown below.

 

BUFGCE.gif

 

Avrum

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-05-2007

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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Example of BUFR dividing clock by 4 to form a regional clock. You could always follow with a BUFG to make a global clock if the logic does not fit within a region.

 

 

--

--

-- The Unisim Library is used to define Xilinx primitives. It is also used during

-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd

--

library unisim;

use unisim.vcomponents.all;

--

 

 

--

-----------------------------------------------------------------------------------------

-- Create 50MHz clock from 200MHz differential clock

-----------------------------------------------------------------------------------------

--

 

diff_clk_buffer: IBUFGDS

port map ( I => clk200_p,

IB => clk200_n,

O => clk200);

 

--

-- BUFR used to divide by 4 and create a regional clock

--

 

clock_divide: BUFR

generic map ( BUFR_DIVIDE => "4",

      SIM_DEVICE => "7SERIES")

port map ( I => clk200,

O => clk50,

CE => '1',

CLR => '0');

 

Ken Chapman
Principal Engineer, Xilinx UK
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Observer carven
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Registered: ‎02-09-2011

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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hi florentw,

and how about the corresponding timing constraints? Just set the clock constraint on the clock input port? or both input and divided clock should be constrained? Thanks!
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Historian
Historian
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Registered: ‎01-23-2009

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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and how about the corresponding timing constraints?

 

When you use a BUFGCE to "divide" the clock, it needs constraints. Like all systems, you always constrain the input clock at the port of the FPGA with a create_clock command.

 

For the BUFGCE, you have to tell the tool that the output of the BUFGCE is a derived clock with 1/2 the frequency of the input clock. This is done with a create_generated_clock command. There are a couple of ways to do this - one which seems simpler, and one which is more correct.

 

The simpler one is

 

create_generated_clock -source [get_pins <bufgce_inst>.I] -divide_by 2 [get_pins <bufgce_inst>.O]

 

(where <bufgce_inst> is the instance replaced with the instance name of the BUFGCE.

 

But this isn't entirely accurate - without any additional information, the tool understands this clock to have a 50/50 duty cycle, but in reality it doesn't, the duty cycle is 1/2*N, where N is the divider - so if the BUFGCE is dividing by 2, the duty cycle is 1/4. This can be represented with

 

create_generated_clock -source [get_pins <bufgce_inst>.I] -divide_by 2 -duty_cycle 0.25 [get_pins <bufgce_inst>.O]

 

This is fine in this case, but can be a problem for odd dividers - for example if the divider is 3, then the value would be 0.166..., which can't be represented with infinite accuracy. So the better solution is

 

create_generated_clock -source [get_pins <bufgce_inst>.I] -edges {1 2 5} [get_pins <bufgce_inst>.O]

 

The -edges provides a triplet, which indicates which source edge causes the rising, falling and next rising edge of the generated clock. So in this case the output clock

  - rises at the time of the first source edge (1)

  - falls at the time of the 2nd source edge (2)

  - rises again at the time of the 5th source edge (5)

 

In general, for a divider of N, the triplet would be {1 2 2*N+1}

 

Avrum

 

 

 

Voyager
Voyager
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Registered: ‎06-24-2013

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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@avrumw

 

Care to elaborate why the rather unhealthy 25% duty cycle clock (with all the associated timing problems) the BUFGCE plus counter will generate is preferable over the nice 50% duty cycle the BUFR (with optional BUFG if you need a global clock) produces?

 

Thanks in advance,

Herbert

-------------- Yes, I do this for fun!
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Historian
Historian
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Registered: ‎01-23-2009

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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@hpoetzl,

 

Care to elaborate why the rather unhealthy 25% duty cycle clock (with all the associated timing problems) the BUFGCE plus counter will generate is preferable over the nice 50% duty cycle the BUFR (with optional BUFG if you need a global clock) produces?

 

The BUFR is really intended for I/O clocking, and, in particular, driving the CLKDIV input of the ISERDES and OSERDES. Consequently, it is located in the CMT column, right beside the I/O on the periphery of the chip.

 

If the original (high speed) clock is coming from a global clock resource (a BUFG), then it needs to travel from the clock column (in the center of the die) to the CMT column (on the edge) to get to the BUFR, and then travel back to the center of the die to reach the BUFG. While some of this travel back and forth is through dedicated connections, none of it is PVT compensated. As a result, the skew between your original clock and the divided clock will be quite large and PVT variable.

 

When done this way, your two clock domains (original and divided) must be treated as mesochronous. This will require clock domain crossing circuits any time you need to move data from one domain to the other. Even at (very) low frequencies where you can tolerate this much skew for the setup checks, in one direction (from the original to the divided domain), the hold time requirements will be huge, making it unlikely that the router will be able to fix them - again, requiring clock domain crossing. Every clock domain crossing circuit (which may require clock crossing FIFOs for significant data movement) will require the use of a reasonable number of cells (possibly including RAMs) and will require timing exceptions.

 

Furthermore, going back and forth like this, the clock will be traveling through the FPGA fabric, picking up noise from the surrounding circuitry, resulting in more jitter on the clock.

 

All told, this creates a noisy clock with no known phase relationship to the original, thus requiring clock crossing.

 

Conversely, the BUFGCE solution results in the two clocks being almost perfectly in phase. As a result, you can move freely between the two domains with little problems and with no clock domain crossing. Other than the create_generated_clock, no additional constraints are required to bring data back and forth between the two domains.

 

Yes, this clock as an unusual duty cycle. However, that only matters in 3 cases (only one of which really matters)

  - pulse width checks: Most clocked cells require a high time that is larger than some minimum. Very odd duty cycle clocks may have problems with this. However, in this case, the high time of your divided clock is the same as the high time of your original clock, so if the original clock passes the pulse width check, then so will the divided one

  - using the negative edge of the clock in internal logic: With a 50/50 duty cycle clock, a path from the rising of the clock to the falling edge of the clock and the path from the falling of the clock to the rising edge of the clock both are timed at 1/2 the clock period. With an odd duty cycle, the requirement is less for the rising to falling path than the other way (1/4 vs. 3/4). But, using falling edge internal flip-flops is rare (it is usually bad style). Hence this is rarely an issue

  - using IDDR or ODDR applications: This is a real problem - and you can't use the BUFGCE for cases like this. On the other hand, I wouldn't use the BUFR here either (unless you are using the high performance clock path from an MMCM and the OSERDES) - I would use a divided clock from an MMCM or PLL. Remember, the duty cycle of the BUFR also isn't always 50/50 - for odd dividers, it is uneven (although not as bad as the BUFGCE)

 

The other disadvantage of the BUFGCE solution is that it requires two BUFGs - one for the original clock and one for the divided. However, if you use the BUFR followed by the BUFG, you are still using two (plus the BUFR). Using the BUFR, of course, if you only need the clock in one clock region, then you can skip the second BUFG. But, if you only need the divided clock in one clock region, then you can use a BUFHCE instead of the BUFGCE instead. While used slightly differently (in series with the BUFG, rather than in parallel - see below), this has the same results - a clock that is completely in phase with the non-divided clock on the BUFG, but uses only one BUFG and one BUFH (which are rarely in short supply), but is restricted to one clock region.

 

Avrum

 

BUFHCE.gif

 

 

Scholar ronnywebers
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Registered: ‎10-10-2014

Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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@avrumw, referring to your first schematic (with BUFGCE in parallel with BUFG) : I did draw a timing diagram uisng a 2-bit counter, with terminal count set to b'11' (tc <= cnt_q0 and cnt_q1)

 

if I'm correct that would generate a slowClk that looks like this :

 

ideal timing.png

 

now this is all drawn with 'ideal' timing : zero delay FF's, zero delay AND gate and zero routing delay. Now I was wondering what happens in reality, where the counter FF's have some delay, as well as the AND gate that generates the terminal count at value b'11' ... If I draw this, I get :

 

real timing.png

 

as I draw it here with 'real delays', that would give '2 clock spikes', instead of a nice single clock cycle. I assume my 2nd drawing is incorrect, and that the tools do some 'compensation in routing (?) to allign the CE input of the BUFGCE nicely with the clock signal at the input of the BUFGCE? 

 

ps.: I just discovered this great and free tool to draw these timing diagrams quickly

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Visitor lclausen
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Re: How to divide a clock by 2 with a simple primitive, without Clock Wizard? (Artix-7)

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@ronnywebers I was just looking into the same and found the follwing in UG472 "Series7 clocking guide"

If the CE input is Low prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. Any level change of CE during the incoming clock High pulse has no effect until the clock transitions Low. The output stays Low when the clock is disabled. However, when the clock is being disabled it completes the clock High pulse.

So it seems the positive pulse will either not go through at all (if CE is low during the rising edge) or completely (if CE is high during the rising edge), even if CE goes low while the input clock is high.