01-03-2019 03:57 PM
01-03-2019 09:21 PM - edited 01-03-2019 09:27 PM
You can swap them with a scalpel, some 30 gauge wire and a soldering iron.
These pins are not part of the "PL" FPGA fabric. They cannot be reprogrammed by any constraints file.
Here's something you can do though - configure your FSBL to make the Zynq use 16 bit RAM instead of 32 bit RAM. I'm reasonably sure that this means it will not drive DM and DM, so their swap becomes irrelevant. You will lose half your RAM capacity (and some speed, due to reduced bus width), but at least you can get your board working well enough to test the rest of it while you wait for your revised PCB design to be manufactured.
BTW, you might want to check chapter 10 of the Zynq 7 TRM ug585 to make sure that 16 bit mode really will work for you.
01-07-2019 09:20 AM
Thanks Allanherriman for your suggestion of configure the DDR memory to 16 bit wide in the FSBL. I will try this at some point soon. Another method I'm thinking of making a small PC board with the two pin correction and stack the DDR3 memory on it and solder the small PCB with the DDR3 memory stacked on it on my main PCB.