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Adventurer
Adventurer
120 Views
Registered: ‎07-05-2017

How to swap DDR memory Controller pins on ZYNQ FPGA?

On a XC7Z020-1CLG484C FPGA
 
I am using the pre-packaged IP DDR3 memory controller off the Zynq processor. I made a mistake on copying the reference design from the Zedboard on two DDR3 interface pins,  DDR3-DM2 and DDR3-DM3 that are fixed on P1 and AA2 respectively on ZYNQ FPGA IO bank 502. 
 I looked at the I/O ports selection gui in "ELABORATED DESIGN" and it seems like they are fixed. Is there a way to swap the  DDR3-DM2 and DDR3-DM3 pin selection from (P1 , AA2) to (AA2,  P1)?  Where can I find the constraint file?
 
Thanks,
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2 Replies
90 Views
Registered: ‎01-08-2012

Re: How to swap DDR memory Controller pins on ZYNQ FPGA?

You can swap them with a scalpel, some 30 gauge wire and a soldering iron.

These pins are not part of the "PL" FPGA fabric.  They cannot be reprogrammed by any constraints file.

 

Here's something you can do though - configure your FSBL to make the Zynq use 16 bit RAM instead of 32 bit RAM.  I'm reasonably sure that this means it will not drive DM[2] and DM[3], so their swap becomes irrelevant.  You will lose half your RAM capacity (and some speed, due to reduced bus width), but at least you can get your board working well enough to test the rest of it while you wait for your revised PCB design to be manufactured.

BTW, you might want to check chapter 10 of the Zynq 7 TRM ug585 to make sure that 16 bit mode really will work for you.

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Adventurer
Adventurer
54 Views
Registered: ‎07-05-2017

Re: How to swap DDR memory Controller pins on ZYNQ FPGA?

Thanks Allanherriman for your suggestion of configure the DDR memory to 16 bit wide in the FSBL. I will try this at some point soon. Another method I'm thinking of making a small PC board with the two pin correction and stack the DDR3 memory on it and solder the small PCB with the DDR3 memory stacked on it on my main PCB.

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