UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor bilkaka
Visitor
4,182 Views
Registered: ‎01-10-2017

How to use GTGREFCLK in the IP core-JESD204_phy on K7?

Jump to solution

In my design I want to use the GTGREFCLK in the JSED204_phy,I modified the CPLLREFCLKSEL to 3'b111,and drove the GTGREFCLK by MMCM(125MHz),but there were some errors when implementated the projection.

 

[DRC 23-20] Rule violation (REQP-52) connects_GTGREFCLK_ACTIVE - GTXE2_CHANNEL cell i_jesd204_0_support_block/i_jesd204_phy/inst/jesd204_phy_block_i/jesd204_0_phy_gt/inst/jesd204_0_phy_gt_i/gt0_jesd204_0_phy_gt_i/gtxe2_i: Use of the GTGREFCLK is reserved for test purposes only. This has the lowest performance of the available clocking methods and can degrade transceiver performance. Note that GTGREFCLK use may be caused by driving a REFCLK with a BUFG.

 

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Visitor bilkaka
Visitor
7,836 Views
Registered: ‎01-10-2017

Re: How to use GTGREFCLK in the IP core-JESD204_phy on K7?

Jump to solution
Hi @vuppala
Thanks for your advice.
I set up the IP core again.
"shared logic in example design",
and in the Synthesis Options , I chose Global.
Then it can be modified.

Thanks,
Bilkaka
3 Replies
Visitor bilkaka
Visitor
4,142 Views
Registered: ‎01-10-2017

Re: How to use GTGREFCLK in the IP core-JESD204_phy on K7?

Jump to solution

I just found that this IP core was not allowed to be modifyied.

when I open the Schematic in Sythesized Design,the CPLLREFCLKSEL[2:0] is still 1'b001.

How can I modify the CPLLREFCLKSEL ?

 

Thanks,

Bilkaka

0 Kudos
Xilinx Employee
Xilinx Employee
4,122 Views
Registered: ‎04-16-2012

Re: How to use GTGREFCLK in the IP core-JESD204_phy on K7?

Jump to solution

Hi @bilkaka

 

Try these steps to change the setting:

  1. Open Synthesized design
  2. Select the GT in the schematic
  3. In Properties window, look for CPLLREFCLKSEL and change its value.

Thanks,

Vinay

--------------------------------------------------------------------------------------------
Have you tried typing your question in Google? If not you should before posting. Also, MARK this is as an answer in case it helped resolve your query/issue.Give kudos to the post that helped you to find the solution.
0 Kudos
Visitor bilkaka
Visitor
7,837 Views
Registered: ‎01-10-2017

Re: How to use GTGREFCLK in the IP core-JESD204_phy on K7?

Jump to solution
Hi @vuppala
Thanks for your advice.
I set up the IP core again.
"shared logic in example design",
and in the Synthesis Options , I chose Global.
Then it can be modified.

Thanks,
Bilkaka