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Interfacing Artix 7 with CMOS image sensors

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Observer
Posts: 18
Registered: ‎12-15-2017
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Interfacing Artix 7 with CMOS image sensors

Hi,

    I've a requirement to interface a CMOS Image sensor(MT9P006) with Artix7 FPGA. I've to perform image processing including autofocus and interfacing with USB 3.0 peripheral controller IC. Is it possible with artix7??? If yes, then what are the tools (like vivado ISE etc) required and what will be the expected cost for those tools... Is there any free software alternatives for them???

 

 

Thank you...


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Adventurer
Posts: 62
Registered: ‎07-18-2011

Re: Interfacing Artix 7 with CMOS image sensors

As far as interfacing goes, yes, the Artix-7 is fine for interfacing with the OnSemi image sensors.  I'm working on an Artix-7 interface to the OnSemi Python 1300 series right now.

 

For Artix-7, you will need the Vivado toolset.   Since the MT9P006 is a parallel CMOS output, you won't have to do anything fancy with LVDS bit alignment or bitslip word alignment, so it should be fairly straightforward, although you will need to read the datasheet very carefully, some of the OnSemi sensors have odd pixel readout sequences.

 

Since this is your first time using Artix for video applications, I recommend you purchase an evaluation board such as the Digilent Nexys Video board available here:  

 

     http://store.digilentinc.com/nexys-video-artix-7-fpga-trainer-board-for-multimedia-applications/

 

it works with the free Xilinx webpack version of Vivado, which supports the XC7A100TFGG484 used on the Nexys board:

 

      https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

 

I don't know what you will need for your image processing functions, so you will have to do further research to determine if the XC7A100 has enough horsepower for your needs.

 

 

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Adventurer
Posts: 62
Registered: ‎07-18-2011

Re: Interfacing Artix 7 with CMOS image sensors

As far as interfacing goes, yes, the Artix-7 is fine for interfacing with the OnSemi image sensors.  I'm working on an Artix-7 interface to the OnSemi Python 1300 series right now.

 

For Artix-7, you will need the Vivado toolset.   Since the MT9P006 is a parallel CMOS output, you won't have to do anything fancy with LVDS bit alignment or bitslip word alignment, so it should be fairly straightforward, although you will need to read the datasheet very carefully, some of the OnSemi sensors have odd pixel readout sequences.

 

Since this is your first time using Artix for video applications, I recommend you purchase an evaluation board such as the Digilent Nexys Video board available here:  

 

     http://store.digilentinc.com/nexys-video-artix-7-fpga-trainer-board-for-multimedia-applications/

 

it works with the free Xilinx webpack version of Vivado, which supports the XC7A100TFGG484 used on the Nexys board:

 

      https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html

 

I don't know what you will need for your image processing functions, so you will have to do further research to determine if the XC7A100 has enough horsepower for your needs.

 

 

Visitor
Posts: 7
Registered: ‎02-27-2018

Re: Interfacing Artix 7 with CMOS image sensors

Hi @reaiken,
I am wondering about your project with Python 1300. How did you manage to physically connect that image sensor to Artix-7.
Did you have to design a custom board to connect the sensor to the available I/O of Artix?

I am interested to design a such a system, and i am having a hard time to understand the connection between image sensor and FPGA board. It will be nice of you if you can hint.

Regards,
Sirac KAYA 

Adventurer
Posts: 62
Registered: ‎07-18-2011

Re: Interfacing Artix 7 with CMOS image sensors

@pollutioncontroltech,

 

Yes, I have a custom board that the sensor connects to via a flat-flex cable.   The LVDS pairs go into a bank on the Aritx that is powered by 2.5V, so it can receive the LVDS data directly.  

 

I designed a custom Python receiver IP block in Vivado to receive the LVDS data from the sensor and convert it into an AXI4-Stream video output to interface with a VDMA to transfer the video data to the MIG for synchronization and processing.   Since the LVDS data  period is so short, the custom IP block has a DDR LVDS interface module that has bit-alignment and word-alignment state machines to recover and time the LVDS data.   The bit-alignment uses IODELAYE2 and ISERDESE2 primitives in a master-slave format to detect the incoming clock period and align the data in the center of the clock window to insure reliable data recovery.

 

 

 

 

Visitor
Posts: 7
Registered: ‎02-27-2018

Re: Interfacing Artix 7 with CMOS image sensors

Great to hear @reaiken !!!
What was your highest data bandwidth ? Did you ever go up to 20Mb/s??
Is there any way you will allow me to see your custom board schematics  etc. ?

Thank you !
Regards,
Sirac.

Adventurer
Posts: 62
Registered: ‎07-18-2011

Re: Interfacing Artix 7 with CMOS image sensors

@pollutioncontroltech,

 

Mine worked up to the max rate of the P1300 with four lanes.   You can use 1, 2, or 4 channels of LVDS, depending on what resolution/vertical rate you need.

 

I'm sorry, I can't post my schematics or FPGA code.   I am a contract design engineer, so the design/code belongs to the company that hired me to do it.

 

Visitor
Posts: 7
Registered: ‎02-27-2018

Re: Interfacing Artix 7 with CMOS image sensors

Thank you @reaiken,
I understand.
I want to use 4 LVDS lane, i currently am working on a custom board design for P1300/0500/0300. They all have 4 LVDS option with 48 pin package. My custom board will be connecting through FMC port of any FPGA board that has LPC FMC, and those board are a bit pricey.That is why your option seemed perfect !

Regards,