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Visitor user4537
Visitor
175 Views
Registered: ‎05-16-2017

Is it valid to sample a slower clock from a faster clock if the edges are aligned.

I have a 20MHz clock and a 400MHz clock.  Both clocks are generated from the same MMCM block.  The phase on both clocks are set to 0 so the edges of the 20MHz clock should be aligned to the edges of the 400MHz clock.  Is it valid to sample the 20MHz clock using the 400MHz clock in order to detect the falling and rising edges of that clock?

Ignoring any skew due to routing, the register (clocked at 400MHz) that samples the 20MHz clock would have 25ns of setup time and 0ns of hold on its input.  From what I understand the flip-flops in the 7-series parts should have no problems with that timing.

I am able to get through syntesis and place and route with no errors.  But when I run a timing report all kinds of signals show up as having setup or hold violations.

When I run a post place and route timing simulation I don't see any errors.

 

__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__^^__ clk_400mhz


______________^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^________________________________________^^^^^^^^ clk_20mhz


__________________^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^________________________________________^^^^ clk_20mhz_d1

__________________________________________________________^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^____ v_reg

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~><~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ d_reg

--d is the data to transfer
--v is the data valid flag (0 = data invalid, 1 = data valid)

p1:  process(clk_400mhz) is begin
    if rising_edge(clk_400mhz) then
        clk_20mhz_d1 <= clk_20mhz;
       
        if some_condition then
            flag <= '1';
            v    <= '1';
        elsif clk_20mhz = '1' and clk_20mhz_d1 = '0' then
            v <= '0';--clear v one cycle after clk_20mhz rising edge.
 end if;

        --register data and valid flag
 if clk_20mhz = '0' and clk_20mhz_d1 = '1' then
            d_reg <= d;
            v_reg <= v;
        end if;
    end if;
end process;


p2:  process(clk_20mhz) is begin
    if rising_edge(clk_20mhz)then
        if v_reg = '1' then
            --do something with d_reg
        end if;
    end if;
end process;

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5 Replies
Historian
Historian
148 Views
Registered: ‎01-23-2009

Re: Is it valid to sample a slower clock from a faster clock if the edges are aligned.

While structurally legal, you shouldn't sample one clock with another clock. Take a look at this post on a synchronous circuit that accomplishes what you need.

Avrum

Visitor user4537
Visitor
132 Views
Registered: ‎05-16-2017

Re: Is it valid to sample a slower clock from a faster clock if the edges are aligned.

So the major difference, between the post you linked to and what I did, was that instead of sampling the slow clock direclty with the fast clock a toggling signal is generated by the slow clock and that signal is sampled by the fast clock.

Your example toggled the signal on the rising edge.  In my case I want to process some logic in the fast clock domain every time the slow clcok falls.  So I could do what you propose by making the signal toggle on the falling edge of the slow clock.

 

Since it seems both approaches are legal.  Is there any major advantage in using the intermediate toggling signal vs sampling the slow clock directly?  I could see that being the case if routing resources were limited between clock nets and flip-flop/LUT data inputs.

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Historian
Historian
122 Views
Registered: ‎01-23-2009

Re: Is it valid to sample a slower clock from a faster clock if the edges are aligned.

I could see that being the case if routing resources were limited between clock nets and flip-flop/LUT data inputs

So, first of all, they are - the routing connections from clock nets to data pins is pretty limited - particularly in the Spartan3/6 architecture. But this is not the main reason why mine is preferred.

My solution is truly "synchronous" whereas yours, isn't really. In my solution, the synchronous timing path goes from a clocked element on one clock to a clocked element on another clock. The two clocks come from the same source and go through a similar clock buffer and clock network, so the two flip-flops have relatively little clock skew.

Your solution comes from the clock net. The route from the clock net to the data pin of the FF does not go (at least entirely) through the global clock network - it jumps off at some point. That point may be earlier or later than the arrival of the clocks at the clock pin, which can lead to setup or hold time problems on the sampling flip-flop on the destination domain.

Basically, mine is "recommended" - yours is not...

In my case I want to process some logic in the fast clock domain every time the slow clcok falls.  So I could do what you propose by making the signal toggle on the falling edge of the slow clock

Yes, that should work. Alternatively, you could use the rising edge and then count off N/2 fast clock periods (where N is the ratio of the two clocks).

Avrum

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Visitor user4537
Visitor
88 Views
Registered: ‎05-16-2017

Re: Is it valid to sample a slower clock from a faster clock if the edges are aligned.

Well that was a pretty good explanation. I will probably take your suggestion.

Just to be sure I will run a timing report and see which way gives more slack.

As for generating the toggle signal, I will stick to generating it from the falling edge of the slow clock, for no other reason than to avoid putting extra counter logic in the fast clock domain.


Thanks for the help.

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Visitor user4537
Visitor
46 Views
Registered: ‎05-16-2017

Re: Is it valid to sample a slower clock from a faster clock if the edges are aligned.

Just to follow up, I ran the post implementation timing report using two methods.

1)  Sampling the 20MHz clock directly from the 400MHz clock to find the falling edge of the 20MHz clock.

2)  Generating a toggling signal on the falling edge of the 20MHz clock and then sampling that signal using the 400MHz clock.

p_tog:  process(clk_20mhz) is begin
    if falling_edge(clk_20mhz) then
        clk_t <= not clk_t;
    end if;
end process;

p1:  process(clk_400mhz) is begin
    if rising_edge(clk_400mhz) then
        clk_t_d1 <= clk_t;
       
        if some_condition then
            v    <= '1';
        elsif clk_t /= clk_t_d1 then
            v <= '0';--clear v one cycle after clk_20mhz falling edge.
        end if;

        --register data and valid flag
        if clk_t /= clk_t_d1 then
            d_reg <= d;
            v_reg <= v;
        end if;
    end if;
end process;

In my case method #2 (sampling the toggle signal) yielded 0.58ns more timing slack when compared to method #1 (sampling the slow clock directly).

 

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