01-11-2019 09:35 AM
We are in the process of conducting Environmental Testing to the new CLIF3 device. We got failure at 50C which I am investigating. It looks like we might have early batch of PCBs soldered with C grade which is not what it is in the final production with I Grade chip.
In the early stage PCB I see from the chip marking the following
The later batch of boards the marking is
Are these FPGA the same? Are these FPGA I grade?
01-11-2019 10:48 AM
Recheck the part marking for the early stage chip. If Xilinx authentic it should be an F"G"B484. We don't make F"P"G packages. Assuming that checks out these are in fact the same I grade FPGAs.
01-11-2019 10:59 AM
01-11-2019 11:03 AM
That actually not good news since what we see that the FPGA from the early batch is failing at 50C ambient when the FPGA junction temperature is 85C. The Later FPGA chip working fine so far under same condition.
01-11-2019 02:53 PM
For the FPGA chip from the second batch I raised the ambient temperature to 55C which put the FPGA at 90C and it failed. The failure is associated with the GTP transceiver. I am running is at 6.38G which is below the Max speed of 6.6G. If this is indeed industrial grade part it should operate fine to junction temperature of 100C correct?
01-11-2019 04:27 PM
That is correct, provided all other datasheet conditions are met. If (for example) VCCINT is dropping below the minimum acceptable level (even just for very short periods, while the average remains acceptable) then no other aspects of the operation (eg. temperature range) are guaranteed.
01-15-2019 09:18 AM
It is difficult to probe the VCCINT when the system is inside the environment chamber and the PCB is inside enclosure. The result of FPGA from the second and later batch that the FPGA is failing at junction temperature of 90C. It is assumed to be GTP failure since we check continuously the Fiber Optic monitoring for data transfer errors. When we start to see FO errors we report the error as Link Failure.
01-15-2019 03:29 PM - edited 01-15-2019 03:30 PM
So it seems thermal noise is much worse in the latter batch and GTs being very noise sensitive probably doesn't help here either. Assuming there are no difference whatsoever between the two boards you are comparing, these types of temperature dependent failures really come back to device timing. Does your design pass the Xilinx timing tools for your device with no issues at all? What I am guessing is happening here is that from your initial post it seems like folks at your place perceived the earlier batch to be a "C" and timed the design to it(up to 85degC) even though both batches are "I" grade. You need to re-run your design through vivado for "I" grade(upto 100degC) and pass timing on it for it for it to successfully operate up to the 100degC "I" grade max Tj temp. Now you may counter back by saying but why are the earlier batch working? Well I am not sure what the count is per you definition of "batch" but you may have just gotten lucky with that lot and gotten a higher performing part since Xilinx bins their silicon that way.