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Observer rickwebb38
Observer
1,056 Views
Registered: ‎01-18-2018

Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi,

We use a Kintex-7 to create three master SPI interfaces. The SCLK outputs either have one, two or three LVCMOS ADC/DAC loads. Looking at the signal integrity of the SCLK at the device receivers, the SCLK gets progressively worse when more receivers are connected. With the three load case (4pF input capacitance per receiver), we changed the Drive strength from 4mA to 8mA, then 16mA and the resulting SLCK waveform didn't change. The frequency of the SCLK is 31.25MHz, making the period 32ns, but the rise and fall times of the SCLK at the receivers is around 4-6ns. We adjusted the slew setting from Slow to Fast and this made no difference either.

 

With 4mA drive strength and slew rate=Slow, we got:

AD5024_SPI_SCLK_IC1601000.png

This should be a clean square wave of 31.25MHz and LVCMOS33 levels.

 

With 8mA drive strength and slew rate=Fast, we got:

AD5024_SPI_SCLK_IC1601_8mA000.png

 

and with 16mA drive strength and slew rate=Fast, we got:

AD5024_SPI_SCLK_IC1601_16mA000.png

 

I expected the rise and fall times to sharpen up with increasing drive strength but this is not the case.

 

The comments from our FPGA engineer are as follows:

 

"The constraints and pins for the 3 clocks in question.

 

set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS33 DRIVE 16 SLEW FAST} [get_ports aout_ad5024_sclk]

set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS33 DRIVE 16 SLEW FAST} [get_ports ain_ad7924_sclk]

set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS33 DRIVE 16 SLEW FAST} [get_ports ain_ad7266_sclk]

 

The settings we tried were…

 

DRIVE = 4, 8 and 16

SLEW = SLOW and FAST

 

We also tried to adjust

 

set_property LOAD 50 [get_ports aout_ad5024_sclk]

set_property LOAD 50 [get_ports ain_ad7924_sclk]

set_property LOAD 50 [get_ports ain_ad7266_sclk]

 

The settings we tried were…

 

LOAD = 20 and 50

 

Also mention that the sclks are not constrained in the design as clocks, they are outputs of ‘data’ and therefore have no defined set_input_delay or set_output_delay constraints against a constrained sclk. As such, they are not associated with the system clock and are constrained at the pin with the following false path constraint.

 

set_output_delay -clock clk_125mhz 0 [get_ports aout_ad5024_sclk]

set_false_path -from [get_clocks clk_125mhz] -to [get_ports aout_ad5024_sclk]

 

set_output_delay -clock clk_125mhz 0 [get_ports ain_ad7924_sclk]

set_false_path -from [get_clocks clk_125mhz] -to [get_ports ain_ad7924_sclk] 

 

set_output_delay -clock clk_125mhz 0 [get_ports ain_ad7266_sclk]

set_false_path -from [get_clocks clk_125mhz] -to [get_ports ain_ad7266_sclk]

"

 

There is also no mention of the "set_property LOAD" in any documentation, so unsure what this does?

 

Suggestions on the above welcome?

 

Regards,

rickwebb38

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Observer rickwebb38
Observer
1,142 Views
Registered: ‎01-18-2018

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Mark,

 

We changed our FPGA SCLK drive strengths to 16mA for the 31.25MHz clocks. This cleaned up the edges nicely and I've now repeated all the timing measurements at each ADxxxx receiver pin and all meet timing now, so job done!

 

I had to use very short tails (30mm) on the tip of the 2.5G probe to get good results, as tails of 3-4 inches added to the problem, due to the inductance introduced.

 

Thanks for your input on this issue.

 

Regards,

 

Rick.

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13 Replies
1,032 Views
Registered: ‎06-21-2017

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Are the sender and receivers referencing the same ground?  Are the sender and receivers on the same board or are they at opposite ends of a long cable?  Is SCLK terminated in any way?  Have you considered trying various termination schemes?

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1,029 Views
Registered: ‎01-22-2015

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Rick,

 

LVCMOS is meant to drive other LVCMOS gates - and not 50ohm loads.  Note that the high-logic level of 3.3V for LVCMOS33 placed across a 50ohm load means 3.3/50 = 66mA from ohms law.  Also, the SPI communication specification does not use terminating loads.

 

So, try not using terminations (anywhere) on the LVCMOS lines from the FPGA to your SPI devices.  -and ensure that your oscope impedance is not set to 50ohm.

 

Cheers,

Mark

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Observer rickwebb38
Observer
1,019 Views
Registered: ‎01-18-2018

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Bruce,

The transmitting FPGA is on a separate board and the SCLK goes across a board-to-board connector. The ground system is 'common' throughout the system, albeit they also transition through the same connectors.

SCLK is not terminated on the receiving board, but we do split the signal into three, to feed three separate DAC devices (4pF input capacitance). There is no room on the receiving board for adding termination. The trace lengths are approximately 2inch on the FPGA board and 3inch on the receiving board. There is also an intermediate board between the two that introduces a further 3inch of track. The intermediate board uses a flexi-cable of about 3inch long to reach the receiving board, so about 11inch end-to-end of track plus connector pin lengths!

I did also try using a different scope probe tip arrangement and that showed better results with less discontinuities on the edges of the SCLK, but still not a very good 'square' wave.

All the scope traces were done using a 2.5G Tek scope with 2.5G active probes.

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Observer rickwebb38
Observer
1,016 Views
Registered: ‎01-18-2018

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Mark,

 

Just to clarify, we don't use any termination end to end in the hardware. The scope I used has active 2.5G probes that connect to the scope using the 50ohm impedance.

 

Regards,

 

Rick.

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1,000 Views
Registered: ‎01-22-2015

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Rick,

 

From your original post, it seems you are using the AD5024, AD7266, AD7924 parts.  Datasheets for this parts specify maximum frequency for SCLK of 50MHz, 32MHz, and 20MHz respectively.   Are you trying to clock these parts at 125MHz?

 

Mark

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Observer rickwebb38
Observer
998 Views
Registered: ‎01-18-2018

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Mark,

 

No.

AD5024 = 31.250MHz

AD7924 = 15.625MHz

AD7266 = 31.250MHz

 

Regards,

Rick.

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986 Views
Registered: ‎01-22-2015

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Rick,

 

What does SCLK=15.625MHz look like on the oscope?

 

Can you remove AD7924 from the SPI bus and then look at SCLK=31.250MHz on oscope?

 

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Observer rickwebb38
Observer
968 Views
Registered: ‎01-18-2018

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Mark,

 

Yesterday I hadn't had chance to look at the 15.625MHz SCLK to the AD7924, but it is now attached. Looks clean.

AD7924_SPI_SCLK.png

 

I'll continue looking at the other 31.250MHz interfaces today. It makes a difference on what scope probe tip I use also, however, the solder down tips take more time to get on the board and I have limited space.

 

Regards,

Rick.

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960 Views
Registered: ‎01-22-2015

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Good morning Rick,

 

     …the 15.625MHz SCLK to the AD7924, but it is now attached. Looks clean.

This is very good news!

 

     It makes a difference on what scope probe tip I use also, however, the solder down tips take more time..

Our oldest oscope has 200MHz* bandwidth and is capable of accurately measuring 15MHz and 33MHz clock signals with standard contact probes. You shouldn’t need a special oscope or special solder down tips for this work.

 

Can you also use oscope to check SPI serial data line(s) (SDAT)?

 

After rereading your initial post, it seems you have separate SPI interfaces from the FPGA to each of the three devices. That is, each device has it own SCLK, SDAT, and CS. Is my understanding correct?

 

Mark

 

*CORRECTION:  Our oldest scope has 200MHz bandwidth (not 100MHz).  A bandwidth of 100MHz is not quite enough to accurately measure 33MHz clock signal. 

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Observer rickwebb38
Observer
744 Views
Registered: ‎01-18-2018

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Mark,

 

The AD5024 DAC use one SCLK from the FPGA and it splits into three to drive three AD5024 devices. We then have three separate CS* and three separate MOSI signals, all outputs from the FPGA. The AD5024_SCLK therefore sees three loads.

 

The AD7266 ADC uses one SCLK from the FPGA and it is then buffered by two low skew clock buffers, to create two sets of four SCLKs to eight AD7266 devices. The CS* is buffered in the same way. We then have Common A[2:0] signals to all eight devices and separate MISOA and MISOB signals from the eight AD7266 devices.

 

The AD7924 ADC uses individual SCLK, CS*, MOSI and MISO signals, as there is only one device.

 

The AD7924 signals look fine.

The AD5024 and AD7266 SCLK signals are the ones we are having problems with (hence this post), as I can't seem to clean them up using any of the available settings in the FPGA (Drive strength, Slew). The LOAD attribute we use in the set_property line isn't documented anywhere either, so would be good to know what that does to the output cells.

 

Regards,

Rick.

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727 Views
Registered: ‎01-22-2015

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Rick,

 

The LOAD attribute we use in the set_property line isn't documented anywhere either, so would be good to know what that does to the output cells.

 

Regards your constraint:

     set_property LOAD 50 [get_ports aout_ad5024_sclk]

 

I also use the Kintex-7 and placing a similar constraint in the XDC file produces the following critical warning.

     [Common 17-69] Command failed: Cannot set load on pre-synthesized design. Please open a synthesized

               design (or synthesize the current design) and rerun this command.

 

I can open the synthesized design and successfully issue the constraint (by typing it into the Tcl Console) – but still unsure what it does. However, I am very sure it is NOT placing a 50-ohm termination to ground on your aout_ad5024_sclk port.

 

You may be interested in reading Appendix-A of UG471, which explains OFFCHIP_TERM attribute for a port. Note that this attribute is for noise analysis and does not actually place an “off-chip termination” on the FPGA port.

 

You might also note that LOAD is not shown in Table 1-12 of UG471 that lists allowed attributes for LVCMOS33.

 

It would be nice if Xilinx listed and explained all valid attributes/properties for an Kintex-7 port. There are actually lots (try opening your synthesized design and typing report_property [get_ports aout_ad5024_sclk] into the Tcl Console). -but alas. Maybe a Xilinx moderator will come to our rescue on this.  However, I feel that properly setting the “LOAD” property for your SCLK port is not the solution to your problem.

 

So, back to business…..

 

For SCLK used by AD5024, I understand from your comments to Bruce and I that the path of this clock is(?):

 

      FPGA(1) – traces – splitter(2) – cable – BUFboard(3) – cable – (4)AD5024board

 

Can you use oscope to check SCLK at various points in this path?  Also, check SCLK after disconnecting things from the path (eg. uplug the AD5024board)? 

 

Also, I still think it important to check data lines (MISO, MOSI) with your oscope. 

 

Cheers,

Mark

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Registered: ‎01-22-2015

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Rick,


Through experimentation in Vivado, I find that the following two Tcl commands seem to be equivalent:
    set_property LOAD 50 [get_ports <port name>]
    set_load 50 [get_ports <port name>]

That is, they both change the LOAD property for a port of the Kintex-7.  

 

UG835 describes the set_load command as follows:

Sets the load capacitance on output ports to the specified value. The load capacitance is used during power analysis when running the report_power command, but is not used during timing analysis.


Finally, I find that the set_load command can be placed in the XDC file and not cause warnings or errors during synthesis and implementation.

 

Mark

 

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Observer rickwebb38
Observer
1,143 Views
Registered: ‎01-18-2018

Re: Kintex 7 drive strength/Slew control makes no difference to SPI SCLK output

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Hi Mark,

 

We changed our FPGA SCLK drive strengths to 16mA for the 31.25MHz clocks. This cleaned up the edges nicely and I've now repeated all the timing measurements at each ADxxxx receiver pin and all meet timing now, so job done!

 

I had to use very short tails (30mm) on the tip of the 2.5G probe to get good results, as tails of 3-4 inches added to the problem, due to the inductance introduced.

 

Thanks for your input on this issue.

 

Regards,

 

Rick.

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