LVDS_25 with too large amplitude

[srdjan.opacic]

my customer built a custom board with 2 Kintex7, connected over LVDS_25 link. The link is working, but my customer is measuring too large LVDS amplitude, outside specified range. LVDS is terminated with internal terminations, measurement is done on vias under the receiving FPGA.

The values he measures are very similar to the ones reported in the post below:

https://forums.xilinx.com/t5/7-Series-FPGAs/Artix-7-MINI-LVDS-25-output-seems-to-be-exceeding-spec/td-p/738149

Could this be a related problem? i see that this older post never really explained the too-large amplitude. Any help would be appreciated.

Thanks

Srdjan

[tenzinc]

Srdjan.opacic,

How are you measuring the "too large amplitude"? If you are talking about Vodiff, it can be larger as long as it is within the Vin spec. 

Regards,

T

[bpatil]

Hello @srdjan.opacic

I will suggest you to get scope-shots from customer and also how he is measuring voltage of LVDS signal (Single ended mode or differential mode of oscilloscope). Once this data is available with you then https://forums.xilinx.com/t5/7-Series-FPGAs/Artix-7-MINI-LVDS-25-output-seems-to-be-exceeding-spec/td-p/738149 mentions details of how single ended or differential ended measurement co-relates each other and also how to check its matching datasheet specifications or not. 

[srdjan.opacic]

Hi,

Sorry for the late reply; As far as I can see, both V_ODIFF and V_IDIFF have the same range, maximum differential should be 600 mV. See table below from DS182.

[srdjan.opacic]

Hi @bpatil,

Sorry for the late reply. I checked the doc you mentioned, I assume you mean that i have to check if my customer is measuring actual Vdiff, or absolute voltage. he is measuring Vdiff, here is his oscillogram; as you can see, Vdiff ranges between +424mV and -408mV.

Best regards

Srdjan

[watari]

Hi @srdjan.opacic

Would you share an external termination register value for LVDS ?

Best regards,

[srdjan.opacic]

Hi @watari,

I'm not sure I understand, I use internal termination in the receiving Kintex7. Here is snippet from my XDC;

set_property IOSTANDARD LVDS_25 [get_ports {lvds_in_?_lvds_data_in_?[?]}]
set_property IOSTANDARD LVDS_25 [get_ports {lvds_in_?_lvds_clk_in_?}]
set_property DIFF_TERM true [get_ports {lvds_in_?_lvds_data_in_?[?]}]
set_property DIFF_TERM true [get_ports {lvds_in_?_lvds_clk_in_?}]

Best regards

Srdjan

[watari]

Hi @srdjan.opacic

Got it. You use an internal termination in XDC file.

BTW, I suspect you use both termination (an internal termination and an external termination).

Would you share the schematic around LVDS Rx ?

Best regards,

[gnarahar · Accepted solution]

@srdjan.opacic Since I authored the solution post of the forum post you referred to, let me take a shot at this.

The scope shots looks fine and is within range. Why do you think it is above spec or very large? The scopeshot you shared is Differential and shows how high P is over N (424mV) or N is over P (408mV) and 832mV Peak-Peak. So what you measure is 2 times (Q-Qbar) of the spec we mention. 

Our spec in Table 12 you referred earlier, mentions how High P should be over N or N over P. The Max swing is 600mV (you are only at 400mV) at 1.425V common mode. 

Do refer to this post where I explained the spec

[srdjan.opacic]

Hi @watari,

I'm confident I don't have external terminations, I believe the whole problem was simple misunderstanding of the datasheet. Thanks for your help, and sorry to have wasted your time.

Best regards

Srdjan

[srdjan.opacic]

Hi @gnarahar,

Thanks, this cleared the situation. I was thinking in terms of peak-to-peak amplitude, while I should have looked at the absolute value of the differential voltage. Thanks for your help, I'll mark this as solution and close the thread.

Best regards

Srdjan