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767 Views
Registered: ‎08-07-2018

LVDS ADC DATA CAPTURE WITH ZED BOARD

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hi..

 

I am using zedboard to capture LVDS data output from one of the TI EVM -AFE5809. I wrote VHDL code including select_io_wizard IP .ADC is of 14bit resolutuon  For every possible data output combination there is always one high-speed bit clock and one sample rate frame clock available.Since sampling is taking place at both rising and falling edge of bit clock ,configured select_io_wizard in DDR Mode.

 

when i ma giving all '0's and all '1 's apttern at ILA its able to get .but when i am giving other signals using the GUI of afe5809 for eg. toggle pattern and ramp pattern ,i m not able to get correct wavform at ILA.

 

Attaching the timing diagram and my vhdl code.

pls help me to resolve the issue . EVM is working fine as per Texas instruments verification .  I wrote another vhdl (main.vhd-in attached files)code  using serial to parallel shift register .tat also not working fine

 

 

thanks in advance

sangeetha

timing_dgrm_adc.PNG
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1 Solution

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Moderator
Moderator
815 Views
Registered: ‎04-18-2011

Re: LVDS ADC DATA CAPTURE WITH ZED BOARD

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The wizard will only build for you the basic structure needed to capture the data. 

To properly capture this data you have to consider the position of the sample clock in the data eye. So you must use the delay line dynamically adjust the clock so that it gets re-positioned in the data eye. 

once you have done this you will need to use the frame clock you send to detect the word alignment of the data and bitslip the ISERDES so that you get the 14 bit samples properly aligned. 

 

Luckily, we have an application note you can refer to. 

http://www.xilinx.com/support/documentation/application_notes/xapp524-serial-lvds-adc-interface.pdf

 

Please take a look and see if it helps. 

 

Keith 

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5 Replies
Moderator
Moderator
816 Views
Registered: ‎04-18-2011

Re: LVDS ADC DATA CAPTURE WITH ZED BOARD

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The wizard will only build for you the basic structure needed to capture the data. 

To properly capture this data you have to consider the position of the sample clock in the data eye. So you must use the delay line dynamically adjust the clock so that it gets re-positioned in the data eye. 

once you have done this you will need to use the frame clock you send to detect the word alignment of the data and bitslip the ISERDES so that you get the 14 bit samples properly aligned. 

 

Luckily, we have an application note you can refer to. 

http://www.xilinx.com/support/documentation/application_notes/xapp524-serial-lvds-adc-interface.pdf

 

Please take a look and see if it helps. 

 

Keith 

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Contributor
Contributor
640 Views
Registered: ‎10-31-2017

Re: LVDS ADC DATA CAPTURE WITH ZED BOARD

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does XAPP524 support SDR mode only?

I have tested XAPP524 on my board,  but the output is error.

my adc is AFE5818, 16bit serial lvds, DDR mode, dclk frequency is 8x as fclk 

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Visitor skidmark
Visitor
612 Views
Registered: ‎08-29-2018

Re: LVDS ADC DATA CAPTURE WITH ZED BOARD

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Hi,

 

XAPP524 supports DDR by using 2 instances ISERDESE2 in SDR mode, one working with the sampling clock, one working with the negated version of it.

One instance will therefore capture odd bits, and the other even bits.

 

Best regards

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244 Views
Registered: ‎08-07-2018

Re: LVDS ADC DATA CAPTURE WITH ZED BOARD

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Hello ,

I have tried wtout using serdese . What I did is after converting the differential data input pair ,frame clk, and bit clk into single neded using ibufds ,i have added one IDDR module, whre i used bit clk as one bit clk input and clk_en (CE) i generated based on frame clk . Then the two outputs Q1 and Q2 of IDDR i have stored into a parallel 14 bit buffer using SIPO.SIPO process is controlled using DCLK so for every rising edge of bit clk (DCLK) i m getting two output bits and pushing into a 14 bit buffer . After this stage i have added one fifo where i tried to store the sipo buffer output .

 

When I m trying to give sample waveforms from the AFE5809EVM like a toggle pattern i m getting slightly distorted toggle pattern(edges are not sharp) also observing delays to individual bits when observing in chipscope . The output before FIFo stage and after FIFO stage both are having delays (phase shift) ,Can someone help to resolve this ? attaching my output waveform a for atoggle input AFE5809_OUTPUT.PNG

attaching my test code also for reference .can anyone help to resolve this issues. xapp524 app note is little bit confusing and not able to understand things correctly

 

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Visitor xycfwrj
Visitor
62 Views
Registered: ‎01-25-2019

Re: LVDS ADC DATA CAPTURE WITH ZED BOARD

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Hope you have solved this problem. After studying your screenshots, I think it works.

You see, your adc samples at 50Msps, and I guess you use ILA to capture the waveform with  200MHz or greater sampling speed. So it captures the transition state and the edge is not sharp.

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