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Master Constraints File for xc7vx980t

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Visitor
Posts: 9
Registered: ‎02-09-2018
Accepted Solution

Master Constraints File for xc7vx980t

Hi,

 

Could anyone help me to get the Master Constraints File (XDC Listing) for xc7vx980t FPGA device.

 


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Community Manager
Posts: 259
Registered: ‎08-08-2007

Re: Master Constraints File for xc7vx980t

The Master XDC for the VC707 is specifically for that board and what is populated and connected to the FPGA on that board. 

 

The generic list of Pin is in the ASCII file link I sent you previsouly. Say you are using a FFG1926 package the file is :  https://www.xilinx.com/support/packagefiles/v7packages/xc7vx980tffg1926pkg.txt

 

Then you can see in the Packaging Guide Table 1-12 the description of the functionality of the pins : 

http://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf

 

For example there are two types of Clock inputs MRCC (multi region clock capable) and SRCC (single region clock capable). If you look in the ASCII file then you can see the IOs that are MRCC or SRCC. 

 

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Community Manager
Posts: 259
Registered: ‎08-08-2007

Re: Master Constraints File for xc7vx980t

I'm not sure what a Master Constraints file is. The demo boards have Master Constraint files but that is with the specific pinout for the board.

If you want the ASCII file that lists the pins and their functionality you can find them (for each package) here: 

https://www.xilinx.com/support/package-pinout-files/virtex-7-pkgs.html

 

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Don’t forget to reply, kudo, and accept as solution.
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Visitor
Posts: 9
Registered: ‎02-09-2018

Re: Master Constraints File for xc7vx980t

[ Edited ]

I want to know the clock and I/O pins for the xc7vx980t device.
Something like the list in VC707 Evaluation Board for the Virtex-7 FPGA User Guide.

For example, xc7vx485t has the pins E18 and E19 for the system clock.

Highlighted
Community Manager
Posts: 259
Registered: ‎08-08-2007

Re: Master Constraints File for xc7vx980t

The Master XDC for the VC707 is specifically for that board and what is populated and connected to the FPGA on that board. 

 

The generic list of Pin is in the ASCII file link I sent you previsouly. Say you are using a FFG1926 package the file is :  https://www.xilinx.com/support/packagefiles/v7packages/xc7vx980tffg1926pkg.txt

 

Then you can see in the Packaging Guide Table 1-12 the description of the functionality of the pins : 

http://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf

 

For example there are two types of Clock inputs MRCC (multi region clock capable) and SRCC (single region clock capable). If you look in the ASCII file then you can see the IOs that are MRCC or SRCC. 

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Visitor
Posts: 9
Registered: ‎02-09-2018

Re: Master Constraints File for xc7vx980t

Thank you.
That helped me.

But, what is the difference between using MRCC and SRCC?
Moderator
Posts: 1,504
Registered: ‎07-23-2015

Re: Master Constraints File for xc7vx980t

@elsayed.abdellah


But, what is the difference between using MRCC and SRCC?

MRCC -> Multi-region clock-capable I/O 

SRCC -> Single-region clock-capable I/O 

 

Take a look at Table 1-1 from Page#24 of UG472 which has more details. 

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