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Observer labluxor8
Registered: ‎08-31-2017

Really strange clocking wizard shifting behavior

Hi everybody,

I'm writing about a really odd behavior on my implemented design on a ZedBoard board (and Vivado 2017.4).

I designed such a system (very simplified description):

- the FPGA receives a 10 MHz clock from an external source
- the clock feeds a MMCM and generates two different clocks at 100 and 200 MHz (zero phase setting and duty cycle 50%)
- a custom block uses this two clocks to do something like this: assert or deassert four different outputs (say A, B, C and D) depending on the input data.
- The input data is represented by an std_logic_vector(2 downto 0) where bits 2 and 1 are used to set port A and B (if '00' or '11' then A<='0' and B<='0', if '01' then A<='1' and B<='0', if '10' then A<='0' and B<='1') and bit 0 is used to set port C and D (if '0' then C<='1' and D<='0', if '1' then C<='0' and D<='1'). After a clock cycle all the ports are set to '0' and the new set will be done after some clock cycle (set by a dedicated counter).
- The input data vector comes from two different AXI GPIO blocks which are set from dedicated SDK software.
- There are also other blocks which do some stuff using the same 100/200 clock, asserting-deasserting some outputs.


This is what magically happens. The data on the bit0 change the main clocks phase.
Switching between bit0 = '0' and bit0 = '1' introduce a clock shift of about 800 ps. The phase shift is equally applied to both the 100 and the 200 MHz clock, i.e. to all the signals of the design. With a fast change on the bit0 value all the system is crazly bouncing forward and back (+800 ps, - 800 ps)! I measured this phase shift with an oscilloscope looking at the original 10 MHz external clock and an output signal from the FPGA.

I really don't know how this is possibile. I tried to re-generate all the IP-cores or tried with another ZedBoard but nothing changed.

How can a '0' or '1' value act on the MMCM?!?
Thank you very much,


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