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240 Views
Registered: ‎05-09-2018

Using unused XADC pins for general purpose I/O

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I have an Avnet MicroZed board with a Zynq xc7z020 FPGA.

I am using the XADC in the dual-ADC sequence mode and I am using 5 pairs of Aux ADC inputs: Vaux0:4 and Vaux8:12

I am not using Aux ADC inputs Vaux5:7 and Vaux13:15

In the top level block diagram I have pins J20  (IO_L17P_T2_AD5P_35) and H20 (IO_L17N_T2_AD5N_35) connected as inputs.

However is does not seem to work. I toggle these input pins, but in chipscope the corresponding signals do not move.

Is it possible to use these unused XADC channel pins if I am using other channels on the XADC?

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
231 Views
Registered: ‎08-25-2010

回复: Using unused XADC pins for general purpose I/O

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Hi bakers@esi.com

It's possible to use the mixture of analog and digital I/O. What if these pins are used as outputs?

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Xilinx Employee
Xilinx Employee
232 Views
Registered: ‎08-25-2010

回复: Using unused XADC pins for general purpose I/O

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Hi bakers@esi.com

It's possible to use the mixture of analog and digital I/O. What if these pins are used as outputs?

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Moderator
Moderator
205 Views
Registered: ‎09-18-2014

Re: Using unused XADC pins for general purpose I/O

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Bakers@esi.com

 

AD pins are multi-function pins. They should be usable as digital IO if you do not require them for the ADC implementation. Remember that the auxiliary analog inputs are automatically enabled when the XADC is instantiated so make sure these two pins are also not connected to the XADC at the top level. Another thing is to make sure that you constrain the pins. That means "LOCing" them to a package pin and assigning them an IOSTANDARD compatible with IO bank 35 VCCO. Also the other thing is to make sure your chip-scope is set up correctly. 

 

Regards,

Tezz

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168 Views
Registered: ‎05-09-2018

Re: Using unused XADC pins for general purpose I/O

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Thanks, I updated my .xdc file and it is working now

set_property PACKAGE_PIN J20 [get_ports {A}]
set_property IOSTANDARD LVCMOS18 [get_ports {A}]

set_property PACKAGE_PIN G19 [get_ports {B}]
set_property IOSTANDARD LVCMOS18 [get_ports {B}]

 

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