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Virtex 7 IDELAY AND IDELAYCTRL INSTANTIATION

Visitor
Posts: 3
Registered: ‎07-20-2010

Virtex 7 IDELAY AND IDELAYCTRL INSTANTIATION

Hi,

I have a preliminary design where I have a set of IDELAY modules along with one IDELAYCTRL instantiated in another module "TOP". Now this module "TOP" is instantiated 8 times in the design. I have defined a iodelay group for each instantiation of "TOP" which in this case is u_adc_port. 

 

INST "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_33" IODELAY_GROUP = adc_1_port_0_grp;
INST "u_adc_dac_tst/u_adc_interface/u_adc_port_1/U_33" IODELAY_GROUP = adc_1_port_1_grp;
INST "u_adc_dac_tst/u_adc_interface/u_adc_port_2/U_33" IODELAY_GROUP = adc_1_port_2_grp;
INST "u_adc_dac_tst/u_adc_interface/u_adc_port_3/U_33" IODELAY_GROUP = adc_1_port_3_grp;

INST "u_adc_dac_tst1/u_adc_interface/u_adc_port_0/U_33" IODELAY_GROUP = adc_2_port_0_grp;
INST "u_adc_dac_tst1/u_adc_interface/u_adc_port_1/U_33" IODELAY_GROUP = adc_2_port_1_grp;
INST "u_adc_dac_tst1/u_adc_interface/u_adc_port_2/U_33" IODELAY_GROUP = adc_2_port_2_grp;
INST "u_adc_dac_tst1/u_adc_interface/u_adc_port_3/U_33" IODELAY_GROUP = adc_2_port_3_grp;

 

While running PAR for the design, the following are the errors the arise during the mapping phase:

 

map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst1/u_adc_interface/u_adc_port_3/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_2_port_3_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst1/u_adc_interface/u_adc_port_2/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_2_port_2_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst1/u_adc_interface/u_adc_port_1/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_2_port_1_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst1/u_adc_interface/u_adc_port_0/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_2_port_0_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst/u_adc_interface/u_adc_port_3/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_1_port_3_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst/u_adc_interface/u_adc_port_2/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_1_port_2_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst/u_adc_interface/u_adc_port_1/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_1_port_1_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR 

MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_1_port_0_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name.

 

Can you tell me what I am doing wrong here. Also I would also like to know if I have to specify the group name just before instantiation of each IDELAYCTRL module in the design which is 8 times in my design. I have a hierarchical design with the module "TOP" containing instantiations of IDELAYCTRL and IDELAY modules and which is instantiated 8 times.

Thanks

Xilinx Employee
Xilinx Employee
Posts: 3,082
Registered: ‎11-28-2007

Re: Virtex 7 IDELAY AND IDELAYCTRL INSTANTIATION

You need to apply the same IODELAY_GROUP name on all IDELAYs assoiciated with a particular IDELAYCTRL.

 


ajayvenkatesan wrote:

Hi,

I have a preliminary design where I have a set of IDELAY modules along with one IDELAYCTRL instantiated in another module "TOP". Now this module "TOP" is instantiated 8 times in the design. I have defined a iodelay group for each instantiation of "TOP" which in this case is u_adc_port. 

 

INST "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_33" IODELAY_GROUP = adc_1_port_0_grp;
INST "u_adc_dac_tst/u_adc_interface/u_adc_port_1/U_33" IODELAY_GROUP = adc_1_port_1_grp;
INST "u_adc_dac_tst/u_adc_interface/u_adc_port_2/U_33" IODELAY_GROUP = adc_1_port_2_grp;
INST "u_adc_dac_tst/u_adc_interface/u_adc_port_3/U_33" IODELAY_GROUP = adc_1_port_3_grp;

INST "u_adc_dac_tst1/u_adc_interface/u_adc_port_0/U_33" IODELAY_GROUP = adc_2_port_0_grp;
INST "u_adc_dac_tst1/u_adc_interface/u_adc_port_1/U_33" IODELAY_GROUP = adc_2_port_1_grp;
INST "u_adc_dac_tst1/u_adc_interface/u_adc_port_2/U_33" IODELAY_GROUP = adc_2_port_2_grp;
INST "u_adc_dac_tst1/u_adc_interface/u_adc_port_3/U_33" IODELAY_GROUP = adc_2_port_3_grp;

 

While running PAR for the design, the following are the errors the arise during the mapping phase:

 

map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst1/u_adc_interface/u_adc_port_3/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_2_port_3_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst1/u_adc_interface/u_adc_port_2/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_2_port_2_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst1/u_adc_interface/u_adc_port_1/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_2_port_1_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst1/u_adc_interface/u_adc_port_0/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_2_port_0_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst/u_adc_interface/u_adc_port_3/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_1_port_3_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst/u_adc_interface/u_adc_port_2/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_1_port_2_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR  MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst/u_adc_interface/u_adc_port_1/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_1_port_1_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name. New
map ERROR 

MapLib:1114 - IDELAYCTRL symbol "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_33" (output signal=<none>) has IODELAY_GROUP property "adc_1_port_0_grp". But the design does not contain DELAY element with the same IODELAY_GROUP name.

 

Can you tell me what I am doing wrong here. Also I would also like to know if I have to specify the group name just before instantiation of each IDELAYCTRL module in the design which is 8 times in my design. I have a hierarchical design with the module "TOP" containing instantiations of IDELAYCTRL and IDELAY modules and which is instantiated 8 times.

Thanks




Cheers,
Jim
Visitor
Posts: 3
Registered: ‎07-20-2010

Re: Virtex 7 IDELAY AND IDELAYCTRL INSTANTIATION

Hi Jim,

Thanks for the reply. Could you let me know how do I put a different name for each IDELAY module associated with a particular IDELAYCTRL. Do I include it in the module which instantiates a bunch of IDELAY modules along with the associated IDELAYCTRL.

Thanks

 

Ajay

Xilinx Employee
Xilinx Employee
Posts: 3,082
Registered: ‎11-28-2007

Re: Virtex 7 IDELAY AND IDELAYCTRL INSTANTIATION

I assume you have IDELAY's instantiated in each adc_port? If yes, you can set IODELAY_GROUP on them in UCF as well like below.

 

INST "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_idelay1" IODELAY_GROUP = adc_1_port_0_grp; 

INST "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_idelay2" IODELAY_GROUP = adc_1_port_0_grp; 

INST "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_idelay3" IODELAY_GROUP = adc_1_port_0_grp; 

 

 


ajayvenkatesan wrote:

Hi Jim,

Thanks for the reply. Could you let me know how do I put a different name for each IDELAY module associated with a particular IDELAYCTRL. Do I include it in the module which instantiates a bunch of IDELAY modules along with the associated IDELAYCTRL.

Thanks

 

Ajay




Cheers,
Jim
Observer
Posts: 30
Registered: ‎11-02-2012

Re: Virtex 7 IDELAY AND IDELAYCTRL INSTANTIATION


ywu wrote:

I assume you have IDELAY's instantiated in each adc_port? If yes, you can set IODELAY_GROUP on them in UCF as well like below.

 

INST "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_idelay1" IODELAY_GROUP = adc_1_port_0_grp; 

INST "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_idelay2" IODELAY_GROUP = adc_1_port_0_grp; 

INST "u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_idelay3" IODELAY_GROUP = adc_1_port_0_grp; 

 

 


ajayvenkatesan wrote:

Hi Jim,

Thanks for the reply. Could you let me know how do I put a different name for each IDELAY module associated with a particular IDELAYCTRL. Do I include it in the module which instantiates a bunch of IDELAY modules along with the associated IDELAYCTRL.

Thanks

 

Ajay






I met the same problem, but I use Vivado to PR, Should I set  the IODELAY GROUP in XDC? 

Observer
Posts: 30
Registered: ‎11-02-2012

Re: Virtex 7 IDELAY AND IDELAYCTRL INSTANTIATION

In XDC file the command should be like this:

 

set_protperty IODELAY_GROUP IODELAY_MIG [get_cells u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_idelay1]

set_protperty IODELAY_GROUP IODELAY_MIG [get_cells u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_idelay2]

set_protperty IODELAY_GROUP IODELAY_MIG [get_cells u_adc_dac_tst/u_adc_interface/u_adc_port_0/U_idelay3]

...