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Adventurer
Adventurer
287 Views
Registered: ‎09-18-2018

Vivado 12-1411: XADC

Hi,

I get the following waring (that is problem for a lot of errors)

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance Vaux6_0_v_p_IBUF_inst at N15 (IOB_X1Y108) since it belongs to a shape containing instance design_1_i/xadc_wiz_0/U0/AXI_XADC_CORE_I/XADC_INST. The shape requires relative placement between Vaux6_0_v_p_IBUF_inst and design_1_i/xadc_wiz_0/U0/AXI_XADC_CORE_I/XADC_INST that can not be honoured because it would result in an invalid location for design_1_i/xadc_wiz_0/U0/AXI_XADC_CORE_I/XADC_INST. ["/home/Desktop/ISYS_SonicLightening/zybo_adc/zybo_adc.srcs/constrs_1/imports/Documents/masterlayout.xdc":104]

 

This is only happening in the case that I am using both RGB-Leds at the same time with the XADC on my zybo z7-20 board. If I use only one RGB-Led the are no problems!

 

Does someone know why, and how i can solve this problem?

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3 Replies
Xilinx Employee
Xilinx Employee
252 Views
Registered: ‎05-08-2012

Re: Vivado 12-1411: XADC

Hi @helplessguy.

 

From the 7-Series XADC Guide, it appears that no user LOC constraint is expected for the XDAC auxiliary ports. Can you try removing the constraint to N15 and any IOSTANDARD constraint? These should not fail the unconstrained IO check (UCIO-1) DRC, and would be an exception to general I/O behavior. 

https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf#page=29


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Xilinx Employee
Xilinx Employee
172 Views
Registered: ‎05-08-2012

Re: Vivado 12-1411: XADC

Hi @helplessguy.

Did the earlier response help, or did you find another solution? If so, marking this as a solution, and/or indicating how you resolved this could help other users.

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Adventurer
Adventurer
103 Views
Registered: ‎09-18-2018

Re: Vivado 12-1411: XADC

hi @marcb

I am sorry but I really do not know what you want to say to me with your post.

I understand, that there shouldn't be problems.

This warning is going to some errors:

[Place 30-372] Bank 35 has terminals with incompatible standards:
Incompatible Pair of IO Standards: (OUT of IO Standard LVCMOS33) & (IN of IO Standard LVCMOS18) have incompatible Vccs
 The following  terminals correspond to these IO Standards:
SioStd: LVCMOS33   VCCO = 3.3 Termination: 0  TermDir:  Out  Bank: 35 Drv: 12 Placed :
    Term: segment_tri_o[6]
    Term:  segment_tri_o[7]
SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   Bank: 35 Placed :
    Term:  Vaux14_0_v_n
    Term:  Vaux14_0_v_p
    Term:  Vaux6_0_v_n
    Term:  and Vaux6_0_v_p

[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 13 |    25 |     3 | LVCMOS33(3)                                                            |                                          |        |  +3.30 |    YES |     |
| 34 |    50 |     6 | LVCMOS33(6)                                                            |                                          |        |  +3.30 |    YES |     |
| 35 |    50 |     6 | LVCMOS33(2)  LVCMOS18(4)                                               |                                          |        |  +1.80 |    YES |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |   125 |    15 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 13     | samp_led_tri_o[0]    | LVCMOS33        | IOB_X0Y10            | Y12                  |                      |
|        | samp_led_tri_o[1]    | LVCMOS33        | IOB_X0Y12            | T5                   |                      |
|        | samp_led_tri_o[2]    | LVCMOS33        | IOB_X0Y13            | Y11                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34     | segment_tri_o[0]     | LVCMOS33        | IOB_X1Y90            | T14                  |                      |
|        | segment_tri_o[1]     | LVCMOS33        | IOB_X1Y89            | T15                  |                      |
|        | segment_tri_o[2]     | LVCMOS33        | IOB_X1Y88            | P14                  |                      |
|        | segment_tri_o[3]     | LVCMOS33        | IOB_X1Y87            | R14                  | *                    |
|        | segment_tri_o[4]     | LVCMOS33        | IOB_X1Y92            | V12                  |                      |
|        | segment_tri_o[5]     | LVCMOS33        | IOB_X1Y63            | W16                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35     | Vaux14_0_v_n         | LVCMOS18        | IOB_X1Y107           | N16                  |                      |
|        | Vaux14_0_v_p         | LVCMOS18        | IOB_X1Y108           | N15                  |                      |
|        | Vaux6_0_v_n          | LVCMOS18        | IOB_X1Y109           | J14                  |                      |
|        | Vaux6_0_v_p          | LVCMOS18        | IOB_X1Y110           | K14                  |                      |
|        | segment_tri_o[6]     | LVCMOS33        | IOB_X1Y100           | J15                  |                      |
|        | segment_tri_o[7]     | LVCMOS33        | IOB_X1Y112           | H15                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+


maybe you can tell me, that I should change. Hanging still at this problem!

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