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oserdese2 high speed clock - timing error

Accepted Solution Solved
Explorer
Posts: 147
Registered: ‎02-04-2013
Accepted Solution

oserdese2 high speed clock - timing error

[ Edited ]

I would like to run the OSERDESE2 (SDR, data with => 6) with main clock of 100 MHz and high speed clock of 600 MHz. The implementation report timing failure: Intra-Clock Path for the high speed clock within the MMCM. Please see the attached print screen.

 

Is there a solution for this error or am i too close to the limits of the FPGA - 600Mb/s for the -1 device (according to DS181)?

 

Regards

Klemen

 

 

intraclock_path.png

Accepted Solutions
Instructor
Posts: 3,710
Registered: ‎01-23-2009

Re: oserdese2 high speed clock - timing error

Yes, you cannot drive a BUFG at 600MHz in this device.

 

Before we look at the clocking, though, are you sure you can generate a 600MHz SDR output clock from the OBUF - this is pretty fast, and not many I/O standards will be able to manage this frequency. Is there any possibility of using a 300MHz DDR clock to your external device, rather than a 600MHz SDR clock?

 

If your device can't accept the DDR clock, then you have to use a "different" clocking structure, using the "High Performance Clocks". Use MMCM CLKOUT0 (or 1, 2, 3, but not any of the higher ones) to generate the 600MHz clock. Drive this clock directly to the BUFIO and the BUFR (in parallel) - this places the clock on the "High Performance Clock" network - this can run at higher clock rates.

 

The problem with this is that the 100MHz clock (the CLKDIV clock) must be generated by the BUFR using divide by 6. Since it is on a BUFR, all the logic must be restricted to one clock region. This must include the flip-flops driving the low speed side of the OSERDES (the CLKDIV side). If the actual data comes from a global domain (i.e. a 100MHz clock also generated by the MMCM and using a BUFG), then you must perform clock crossing from the BUFG domain to the BUFR domain - this will (at least) need a shallow clock crossing FIFO (the distributed RAMs are well suited to do this).

 

Avrum

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All Replies
Instructor
Posts: 3,710
Registered: ‎01-23-2009

Re: oserdese2 high speed clock - timing error

Yes, you cannot drive a BUFG at 600MHz in this device.

 

Before we look at the clocking, though, are you sure you can generate a 600MHz SDR output clock from the OBUF - this is pretty fast, and not many I/O standards will be able to manage this frequency. Is there any possibility of using a 300MHz DDR clock to your external device, rather than a 600MHz SDR clock?

 

If your device can't accept the DDR clock, then you have to use a "different" clocking structure, using the "High Performance Clocks". Use MMCM CLKOUT0 (or 1, 2, 3, but not any of the higher ones) to generate the 600MHz clock. Drive this clock directly to the BUFIO and the BUFR (in parallel) - this places the clock on the "High Performance Clock" network - this can run at higher clock rates.

 

The problem with this is that the 100MHz clock (the CLKDIV clock) must be generated by the BUFR using divide by 6. Since it is on a BUFR, all the logic must be restricted to one clock region. This must include the flip-flops driving the low speed side of the OSERDES (the CLKDIV side). If the actual data comes from a global domain (i.e. a 100MHz clock also generated by the MMCM and using a BUFG), then you must perform clock crossing from the BUFG domain to the BUFR domain - this will (at least) need a shallow clock crossing FIFO (the distributed RAMs are well suited to do this).

 

Avrum

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Explorer
Posts: 147
Registered: ‎02-04-2013

Re: oserdese2 high speed clock - timing error

Thank you for your suggestions, this solved the problem :)