UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor asmatia
Visitor
730 Views
Registered: ‎03-13-2018

sample DDR data with DDR clock in different clock region

Hi,

I am using VIRTX 7 - XC7V690T-2FF1157L device

I have a design with 24 data bit and one clock (source synchronous). 

the data is DDR meaning it is sampled at the rising edge and in the falling edge of the clock. clock frequency is 350MHz.

all data and clocks are diff pairs.

due to mistake in layout/design my current situation is as follows:

the clock is connected to MRCC pin in clock region area X0Y7 (bank 17, pins P29,P30)

first 12 bit data connected to clock region area X0Y9 (bank 19)

second 12 bit data connected to clock region area X1Y7 (bank 37)

 

If I understood correctly BUFIO cant be used since they are not in the same clock region or adjacent clock region.

What solution can I provide in order to sample the data correctly (clock and data have 0deg phase offset +-100pS this includes source device of the data and clock and the pcb delays), and how to constrain this correctly?

thanks

0 Kudos
6 Replies
Adventurer
Adventurer
722 Views
Registered: ‎05-23-2018

Re: sample DDR data with DDR clock in different clock region

You could use a MMCM to generate a de-skewed version of the Clock on a BUFG. In addition, you could use the IDELAYs to shift data or clock slightly for calibration purposes.

 

Compare https://www.xilinx.com/support/documentation/application_notes/xapp523-lvds-4x-asynchronous-oversampling.pdf and https://www.xilinx.com/support/documentation/application_notes/xapp585-lvds-source-synch-serdes-clock-multiplication.pdf

Scholar dpaul24
Scholar
710 Views
Registered: ‎08-07-2014

Re: sample DDR data with DDR clock in different clock region

@asmatia,

 

Have you tried the other clk buffers?

 

https://www.xilinx.com/support/answers/46505.html

 

 

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Visitor asmatia
Visitor
697 Views
Registered: ‎03-13-2018

Re: sample DDR data with DDR clock in different clock region

Hi,

thanks for reply!!

I am familiar with the clocking resources, I wanted to see if xilinx support or can guide me how to do it with my current state of layout.

0 Kudos
Historian
Historian
678 Views
Registered: ‎01-23-2009

Re: sample DDR data with DDR clock in different clock region

So, first...

 

350MHz DDR is 1.42ns bit period. Since your device has +/-100ps skew, this brings the data eye down to 1.22ns.

 

Even under ideal conditions, this is almost certainly too small to sample statically - you generally need closer to 1.75ns for that to be possible. And the 1.75ns (or so) is only possible if all pins are in the same bank - the BUFMR totally messes up timing (you need to have more like 2.5ns for that solution).

 

Given what you have said, your only solution is an MMCM with BUFG clocking with dynamic calibration. You can take a look at this (general) posting on dynamic calibration...

 

Avrum

Visitor asmatia
Visitor
619 Views
Registered: ‎03-13-2018

Re: sample DDR data with DDR clock in different clock region

Hi,

thanks for the answer.

since placing all the data in the same bank is impossible, and we have to split the bus to 2 different banks.

having said that, from your answer I understand that i have to use BUFG-MMCM solution. 

since I also don't want to use dynamic reconfiguration but use static phase values:

we thought to find the best phase with test pattern + chipscope and changing the phase manually, and test he selected phase in all temperature range.

 

1. do you think this could be a valid solution?

2. do you think its better to have one mmcm with 2 outputs each with a specific phase for each bank? 

3. for the above solution, is there an advantage to have the banks in adjacent clock regions vs. banks not "close" together (like in the same horizontal raw but not in the same column)

4. suppose we found a good phase. Is the solution repeatable for every card manufactured (between different FPGA's)?

 

 

0 Kudos
Historian
Historian
601 Views
Registered: ‎01-23-2009

Re: sample DDR data with DDR clock in different clock region

since I also don't want to use dynamic reconfiguration but use static phase values:

 

I just want to be clear here - you don't need to use "dynamic reconfiguration" - the MMCM has a "dynamic phase shift" port, which allows a very simple interface to dynamically control the phase shift. This is different (and far less complicated) than dynamic reconfiguration.

 

1. do you think this could be a valid solution?

 

No. The whole point of static timing analysis is to prove that an interface will work across all combinations of process, voltage, and temperature (PVT). Here static timing analysis is clear - there is no static value of phase (even a different one for each pin, whether implemented with the MMCM phase shift or the IDELAY) that will work across PVT.  It is precisely this reason that the interface needs to be dynamic.

 

The rest of your questions are all related - there is no static phase that will work. 

 

If you are "close" to getting static timing to work, it is theoretically possible to do "one time" calibration for each board you produce. Doing this will remove the "process" portion of PVT. If the remaining variables (voltage/temperature) don't create enough variability, you may be able to get by. Unfortunately, there is no way to know if this is sufficient - although considering how far you are from meeting static timing with the timing you are asking for, it is almost certain that this will not be sufficient).

 

So, you need to do dynamic calibration. Pretty much period.

 

Avrum

0 Kudos